From patchwork Fri Jan 29 10:04:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 8161711 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7464EBEEE5 for ; Fri, 29 Jan 2016 10:04:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B7667200F0 for ; Fri, 29 Jan 2016 10:04:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4A2C620122 for ; Fri, 29 Jan 2016 10:04:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751795AbcA2KEx (ORCPT ); Fri, 29 Jan 2016 05:04:53 -0500 Received: from albert.telenet-ops.be ([195.130.137.90]:51402 "EHLO albert.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750826AbcA2KEr (ORCPT ); Fri, 29 Jan 2016 05:04:47 -0500 Received: from ayla.of.borg ([84.195.106.123]) by albert.telenet-ops.be with bizsmtp id Bm4l1s00i2fm56U06m4lEX; Fri, 29 Jan 2016 11:04:46 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1aP5v3-0001FQ-Ha; Fri, 29 Jan 2016 11:04:45 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1aP5v4-000145-2x; Fri, 29 Jan 2016 11:04:46 +0100 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v4 2/7] ARM: dts: r8a7779: Add BRG support for SCIF Date: Fri, 29 Jan 2016 11:04:38 +0100 Message-Id: <1454061883-4043-3-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454061883-4043-1-git-send-email-geert+renesas@glider.be> References: <1454061883-4043-1-git-send-email-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the device node for the external SCIF_CLK. The presence of the SCIF_CLK crystal and its clock frequency depends on the actual board. Add the two optional clock sources (S1 and SCIF_CLK for the internal resp. external clock) for the Baud Rate Generator for External Clock (BRG) to all SCIF device nodes. This increases the range and accuracy of supported baud rates on SCIF. Signed-off-by: Geert Uytterhoeven --- v4: - Change one-line summary prefix to match current arm-soc practices, v3: - New. --- arch/arm/boot/dts/r8a7779.dtsi | 39 +++++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 8fddfae13865f536..a0cc08e6295b0396 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -215,8 +215,9 @@ "renesas,scif"; reg = <0xffe40000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF0>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7779_CLK_SCIF0>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -226,8 +227,9 @@ "renesas,scif"; reg = <0xffe41000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF1>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7779_CLK_SCIF1>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -237,8 +239,9 @@ "renesas,scif"; reg = <0xffe42000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF2>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7779_CLK_SCIF2>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -248,8 +251,9 @@ "renesas,scif"; reg = <0xffe43000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF3>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7779_CLK_SCIF3>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -259,8 +263,9 @@ "renesas,scif"; reg = <0xffe44000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF4>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7779_CLK_SCIF4>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -270,8 +275,9 @@ "renesas,scif"; reg = <0xffe45000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF5>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7779_CLK_SCIF5>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -447,6 +453,15 @@ clock-output-names = "extal"; }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: clocks@ffc80000 { compatible = "renesas,r8a7779-cpg-clocks";