From patchwork Mon Feb 15 20:38:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 8318491 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C24A4C02AE for ; Mon, 15 Feb 2016 20:38:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2C79E20382 for ; Mon, 15 Feb 2016 20:38:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 533F020398 for ; Mon, 15 Feb 2016 20:38:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752852AbcBOUil (ORCPT ); Mon, 15 Feb 2016 15:38:41 -0500 Received: from michel.telenet-ops.be ([195.130.137.88]:60786 "EHLO michel.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752759AbcBOUij (ORCPT ); Mon, 15 Feb 2016 15:38:39 -0500 Received: from ayla.of.borg ([84.195.106.123]) by michel.telenet-ops.be with bizsmtp id Jkec1s00C2fm56U06kecfF; Mon, 15 Feb 2016 21:38:37 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1aVPum-0007pc-Ay; Mon, 15 Feb 2016 21:38:36 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1aVPum-0005RY-VP; Mon, 15 Feb 2016 21:38:36 +0100 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: Dirk Behme , Sudeep Holla , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH v3 1/7] ARM: dts: r8a73a4: Add L2 cache-controller nodes Date: Mon, 15 Feb 2016 21:38:29 +0100 Message-Id: <1455568715-20880-2-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1455568715-20880-1-git-send-email-geert+renesas@glider.be> References: <1455568715-20880-1-git-send-email-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device nodes for the L2 caches, and link the CPU node to its L2 cache node. The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as 64 KiB x 16 ways), and located in PM domain A3SM. The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as 64 KiB x 8 ways), and located in PM domain A3KM. Signed-off-by: Geert Uytterhoeven --- v3: - Drop "arm,data-latency" and "arm,tag-latency" properties, as they may not be valid when using virtualization, - Change one-line summary prefix to match current arm-soc practices, v2: - New. --- arch/arm/boot/dts/r8a73a4.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 138414a7d1703781..6583a1dfca1f64c6 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -29,6 +29,7 @@ reg = <0>; clock-frequency = <1500000000>; power-domains = <&pd_a2sl>; + next-level-cache = <&L2_CA15>; }; }; @@ -45,6 +46,22 @@ ; }; + L2_CA15: cache-controller@0 { + compatible = "cache"; + clocks = <&cpg_clocks R8A73A4_CLK_Z>; + power-domains = <&pd_a3sm>; + cache-unified; + cache-level = <2>; + }; + + L2_CA7: cache-controller@1 { + compatible = "cache"; + clocks = <&cpg_clocks R8A73A4_CLK_Z2>; + power-domains = <&pd_a3km>; + cache-unified; + cache-level = <2>; + }; + dbsc1: memory-controller@e6790000 { compatible = "renesas,dbsc-r8a73a4"; reg = <0 0xe6790000 0 0x10000>;