From patchwork Mon Feb 15 20:38:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 8318511 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AE8689F72C for ; Mon, 15 Feb 2016 20:38:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 02FB220384 for ; Mon, 15 Feb 2016 20:38:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E56332038E for ; Mon, 15 Feb 2016 20:38:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752798AbcBOUim (ORCPT ); Mon, 15 Feb 2016 15:38:42 -0500 Received: from laurent.telenet-ops.be ([195.130.137.89]:36676 "EHLO laurent.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752799AbcBOUik (ORCPT ); Mon, 15 Feb 2016 15:38:40 -0500 Received: from ayla.of.borg ([84.195.106.123]) by laurent.telenet-ops.be with bizsmtp id Jkec1s00N2fm56U01keci2; Mon, 15 Feb 2016 21:38:38 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1aVPum-0007pf-9w; Mon, 15 Feb 2016 21:38:36 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1aVPun-0005Ri-0d; Mon, 15 Feb 2016 21:38:37 +0100 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: Dirk Behme , Sudeep Holla , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH v3 3/7] ARM: dts: r8a7791: Add L2 cache-controller node Date: Mon, 15 Feb 2016 21:38:31 +0100 Message-Id: <1455568715-20880-4-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1455568715-20880-1-git-send-email-geert+renesas@glider.be> References: <1455568715-20880-1-git-send-email-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a device node for the L2 cache, and link the CPU nodes to it. The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as 64 KiB x 16 ways). Signed-off-by: Geert Uytterhoeven --- v3: - Drop "arm,data-latency" and "arm,tag-latency" properties, as they may not be valid when using virtualization, - Change one-line summary prefix to match current arm-soc practices, v2: - Drop (incorrect) optional cache-{size,sets,{block,line}-size} properties, as this information is auto-detected, - Integrate linking CPUs to L2 cache into this patch, - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add SYSC PM Domain DT Support". --- arch/arm/boot/dts/r8a7791.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 8910236e64bf93ed..a65910ed5884edfd 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -51,6 +51,7 @@ voltage-tolerance = <1>; /* 1% */ clocks = <&cpg_clocks R8A7791_CLK_Z>; clock-latency = <300000>; /* 300 us */ + next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ operating-points = <1500000 1000000>, @@ -66,9 +67,16 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1500000000>; + next-level-cache = <&L2_CA15>; }; }; + L2_CA15: cache-controller@0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;