| Message ID | 1455568715-20880-5-git-send-email-geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | fdd0dbd8a28612195dfbfb08c404ef5bcfa48e43 |
| Delegated to: | Simon Horman |
| Headers | show |
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 45dba1c79a43c287..9a30f650aa515b80 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -51,9 +51,16 @@ < 937500 1000000>, < 750000 1000000>, < 375000 1000000>; + next-level-cache = <&L2_CA15>; }; }; + L2_CA15: cache-controller@0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;
Add a device node for the L2 cache, and link the CPU node to it. The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as 64 KiB x 16 ways). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v3: - Drop "arm,data-latency" and "arm,tag-latency" properties, as they may not be valid when using virtualization, - Change one-line summary prefix to match current arm-soc practices, v2: - Drop (incorrect) optional cache-{size,sets,{block,line}-size} properties, as this information is auto-detected, - Integrate linking CPU to L2 cache into this patch, - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add SYSC PM Domain DT Support". --- arch/arm/boot/dts/r8a7793.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)