From patchwork Mon Feb 15 21:16:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 8319301 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BFEE2C02AA for ; Mon, 15 Feb 2016 21:17:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 29A1720398 for ; Mon, 15 Feb 2016 21:17:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 46859202E5 for ; Mon, 15 Feb 2016 21:17:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752536AbcBOVRU (ORCPT ); Mon, 15 Feb 2016 16:17:20 -0500 Received: from andre.telenet-ops.be ([195.130.132.53]:60581 "EHLO andre.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752576AbcBOVRM (ORCPT ); Mon, 15 Feb 2016 16:17:12 -0500 Received: from ayla.of.borg ([84.195.106.123]) by andre.telenet-ops.be with bizsmtp id JlH81s00V2fm56U01lH8bH; Mon, 15 Feb 2016 22:17:10 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1aVQW4-00082g-FR; Mon, 15 Feb 2016 22:17:08 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1aVQW5-0004xN-75; Mon, 15 Feb 2016 22:17:09 +0100 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm , Laurent Pinchart Cc: linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC v2 06/11] ARM: dts: r8a7779: Add SYSC PM domains Date: Mon, 15 Feb 2016 22:16:55 +0100 Message-Id: <1455571020-18968-7-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1455571020-18968-1-git-send-email-geert+renesas@glider.be> References: <1455571020-18968-1-git-send-email-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a device node for the System Controller, with subnodes that represent the hardware power area hierarchy. Hook up ARM CPU cores 1-3 to their respective PM domains. Note that ARM CPU core 0 cannot be shut off. Signed-off-by: Geert Uytterhoeven --- v2: - Correct sysc "reg" property (#address/size-cells = 1, not 2), - Change one-line summary prefix to match current arm-soc practices, - Update compatible values. --- arch/arm/boot/dts/r8a7779.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index a0cc08e6295b0396..14b28c225bb3587c 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -34,18 +34,21 @@ compatible = "arm,cortex-a9"; reg = <1>; clock-frequency = <1000000000>; + power-domains = <&pd_arm1>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; clock-frequency = <1000000000>; + power-domains = <&pd_arm2>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; clock-frequency = <1000000000>; + power-domains = <&pd_arm3>; }; }; @@ -591,4 +594,49 @@ "mmc1", "mmc0"; }; }; + + sysc: system-controller@ffd85000 { + compatible = "renesas,r8a7779-sysc"; + reg = <0xffd85000 0x0200>; + + pm-domains { + #address-cells = <2>; + #size-cells = <0>; + + pd_arm1: cpu@1 { + reg = <1 0x41>; + #power-domain-cells = <0>; + }; + + pd_arm2: cpu@2 { + reg = <2 0x42>; + #power-domain-cells = <0>; + }; + + pd_arm3: cpu@3 { + reg = <3 0x43>; + #power-domain-cells = <0>; + }; + + pd_sh: sh@16 { + reg = <16 0x80>; + #power-domain-cells = <0>; + }; + + pd_sgx: sgx@20 { + reg = <20 0xc0>; + #power-domain-cells = <0>; + }; + + pd_vdp: vdp@21 { + reg = <21 0x100>; + #power-domain-cells = <0>; + }; + + pd_imp: imp@24 { + reg = <24 0x140>; + #power-domain-cells = <0>; + }; + }; + }; };