From patchwork Mon Feb 15 21:16:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 8319451 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 35A679FD0B for ; Mon, 15 Feb 2016 21:17:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7C698202E5 for ; Mon, 15 Feb 2016 21:17:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BA7C420392 for ; Mon, 15 Feb 2016 21:17:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751153AbcBOVR1 (ORCPT ); Mon, 15 Feb 2016 16:17:27 -0500 Received: from baptiste.telenet-ops.be ([195.130.132.51]:59152 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752431AbcBOVRL (ORCPT ); Mon, 15 Feb 2016 16:17:11 -0500 Received: from ayla.of.borg ([84.195.106.123]) by baptiste.telenet-ops.be with bizsmtp id JlH81s00c2fm56U01lH8wf; Mon, 15 Feb 2016 22:17:10 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1aVQW4-00082k-GQ; Mon, 15 Feb 2016 22:17:08 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1aVQW5-0004xS-7h; Mon, 15 Feb 2016 22:17:09 +0100 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm , Laurent Pinchart Cc: linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC v2 07/11] ARM: dts: r8a7790: Add SYSC PM domains Date: Mon, 15 Feb 2016 22:16:56 +0100 Message-Id: <1455571020-18968-8-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1455571020-18968-1-git-send-email-geert+renesas@glider.be> References: <1455571020-18968-1-git-send-email-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a device node for the System Controller, with subnodes that represent the hardware power area hierarchy. Hook up the Cortex-A15 and Cortex-A7 CPU cores and L2 caches/SCUs to their respective PM domains. Signed-off-by: Geert Uytterhoeven --- v2: - Change one-line summary prefix to match current arm-soc practices, - Update compatible values. --- arch/arm/boot/dts/r8a7790.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index e40aa6585831c520..3e5a97c70480cbbc 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -52,6 +52,7 @@ voltage-tolerance = <1>; /* 1% */ clocks = <&cpg_clocks R8A7790_CLK_Z>; clock-latency = <300000>; /* 300 us */ + power-domains = <&pd_ca15_cpu0>; next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ @@ -68,6 +69,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1300000000>; + power-domains = <&pd_ca15_cpu1>; next-level-cache = <&L2_CA15>; }; @@ -76,6 +78,7 @@ compatible = "arm,cortex-a15"; reg = <2>; clock-frequency = <1300000000>; + power-domains = <&pd_ca15_cpu2>; next-level-cache = <&L2_CA15>; }; @@ -84,6 +87,7 @@ compatible = "arm,cortex-a15"; reg = <3>; clock-frequency = <1300000000>; + power-domains = <&pd_ca15_cpu3>; next-level-cache = <&L2_CA15>; }; @@ -92,6 +96,7 @@ compatible = "arm,cortex-a7"; reg = <0x100>; clock-frequency = <780000000>; + power-domains = <&pd_ca7_cpu0>; next-level-cache = <&L2_CA7>; }; @@ -100,6 +105,7 @@ compatible = "arm,cortex-a7"; reg = <0x101>; clock-frequency = <780000000>; + power-domains = <&pd_ca7_cpu1>; next-level-cache = <&L2_CA7>; }; @@ -108,6 +114,7 @@ compatible = "arm,cortex-a7"; reg = <0x102>; clock-frequency = <780000000>; + power-domains = <&pd_ca7_cpu2>; next-level-cache = <&L2_CA7>; }; @@ -116,18 +123,21 @@ compatible = "arm,cortex-a7"; reg = <0x103>; clock-frequency = <780000000>; + power-domains = <&pd_ca7_cpu3>; next-level-cache = <&L2_CA7>; }; }; L2_CA15: cache-controller@0 { compatible = "cache"; + power-domains = <&pd_ca15_scu>; cache-unified; cache-level = <2>; }; L2_CA7: cache-controller@1 { compatible = "cache"; + power-domains = <&pd_ca7_scu>; cache-unified; cache-level = <2>; }; @@ -1441,6 +1451,85 @@ }; }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7790-sysc", "renesas,rcar-gen2-sysc"; + reg = <0 0xe6180000 0 0x0200>; + + pm-domains { + #address-cells = <2>; + #size-cells = <0>; + + pd_ca15_scu: scu@12 { + reg = <12 0x180>; + #address-cells = <2>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_ca15_cpu0: cpu@0 { + reg = <0 0x40>; + #power-domain-cells = <0>; + }; + + pd_ca15_cpu1: cpu@1 { + reg = <1 0x41>; + #power-domain-cells = <0>; + }; + + pd_ca15_cpu2: cpu@2 { + reg = <2 0x42>; + #power-domain-cells = <0>; + }; + + pd_ca15_cpu3: cpu@3 { + reg = <3 0x43>; + #power-domain-cells = <0>; + }; + }; + + pd_ca7_scu: scu@21 { + reg = <21 0x100>; + #address-cells = <2>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_ca7_cpu0: cpu@5 { + reg = <5 0x1c0>; + #power-domain-cells = <0>; + }; + + pd_ca7_cpu1: cpu@6 { + reg = <6 0x1c1>; + #power-domain-cells = <0>; + }; + + pd_ca7_cpu2: cpu@7 { + reg = <7 0x1c2>; + #power-domain-cells = <0>; + }; + + pd_ca7_cpu3: cpu@8 { + reg = <8 0x1c3>; + #power-domain-cells = <0>; + }; + }; + + pd_sh: sh@16 { + reg = <16 0x80>; + #power-domain-cells = <0>; + }; + + pd_rgx: rgx@20 { + reg = <20 0xc0>; + #power-domain-cells = <0>; + }; + + pd_imp: imp@24 { + reg = <24 0x140>; + #power-domain-cells = <0>; + }; + }; + }; + qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7790", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>;