From patchwork Wed May 11 05:29:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dirk Behme X-Patchwork-Id: 9065041 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B6112BF440 for ; Wed, 11 May 2016 05:31:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 01CF32015A for ; Wed, 11 May 2016 05:31:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 30BCB20172 for ; Wed, 11 May 2016 05:31:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751287AbcEKFb2 (ORCPT ); Wed, 11 May 2016 01:31:28 -0400 Received: from smtp6-v.fe.bosch.de ([139.15.237.11]:12990 "EHLO smtp6-v.fe.bosch.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751404AbcEKFb0 (ORCPT ); Wed, 11 May 2016 01:31:26 -0400 Received: from vsmta14.fe.internet.bosch.com (unknown [10.4.98.54]) by imta24.fe.bosch.de (Postfix) with ESMTP id 111E8D80219 for ; Wed, 11 May 2016 07:31:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=de.bosch.com; s=2015-01-21; t=1462944685; bh=icFWhIfoJDNnmwaL+dfFAXk///0PFS4A/c4xu/CT9nk=; l=10; h=From:From:Reply-To:Sender; b=xYTsCQUN98JUfuuss/o10LYJRM8jMizD+ccTuPvkqv6DnqGyVexxiILFMRAAXoJ/y duZwTI26Jypx4to3s1po/wDEm/eFDc/MyzsvSaXe+j5ixMGIf6Wa1GA0moj8vf+lY9 YZDkfboAn+LK4sGPUvN7uUlGYcORrqAWwcKCTTR4= Received: from FE-HUB1000.de.bosch.com (vsgw24.fe.internet.bosch.com [10.4.98.24]) by vsmta14.fe.internet.bosch.com (Postfix) with ESMTP id 9F000A40248 for ; Wed, 11 May 2016 07:31:24 +0200 (CEST) Received: from hi-z08if.hi.de.bosch.com (10.34.209.31) by FE-HUB1000.de.bosch.com (10.4.103.107) with Microsoft SMTP Server id 14.3.195.1; Wed, 11 May 2016 07:31:22 +0200 Received: from hi-z08if.hi.de.bosch.com (localhost [127.0.0.1]) by hi-z08if.hi.de.bosch.com (Postfix) with ESMTP id 6B57A625E9E; Wed, 11 May 2016 07:29:41 +0200 (CEST) From: Dirk Behme To: Geert Uytterhoeven , Simon Horman , CC: Dirk Behme Subject: [PATCH v2 09/10] ARM: dts: r8a779x: Add reset module support Date: Wed, 11 May 2016 07:29:37 +0200 Message-ID: <1462944578-1220-10-git-send-email-dirk.behme@de.bosch.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1462944578-1220-1-git-send-email-dirk.behme@de.bosch.com> References: <1462944578-1220-1-git-send-email-dirk.behme@de.bosch.com> MIME-Version: 1.0 X-TM-AS-MML: disable X-TM-AS-Product-Ver: IMSS-7.1.0.1679-8.0.0.1202-22312.006 X-TMASE-MatchedRID: X6QxN4fiJm/Lqx3pQDUvTgPZZctd3P4B2IrsB0SHqU2wucNx4BfFIkd0 Rzx07LDV96TYN1fO8g6y9AsAxk+TJTlyVH8jNStNxEwSTOeVUQ72QoeyDfGuAIWJP3XdGAwudo+ jVIL0LKPi8zVgXoAltsIJ+4gwXrEtIAcCikR3vq8U3balm55Cq65m5OLeCUGs9FbFGhKuernMgo 9GGWvaEOoff0cniE89 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dirk Behme The reset module on RCar Gen2 and Gen3 SoCs contains various reset handling related registers. Their content is implementation dependent. Signed-off-by: Dirk Behme --- .../devicetree/bindings/misc/renesas,rcar-rst.txt | 15 +++++++++++++++ arch/arm/boot/dts/r8a7790.dtsi | 5 +++++ arch/arm/boot/dts/r8a7791.dtsi | 5 +++++ arch/arm/boot/dts/r8a7793.dtsi | 5 +++++ arch/arm/boot/dts/r8a7794.dtsi | 6 ++++++ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 5 +++++ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 5 +++++ 7 files changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/renesas,rcar-rst.txt diff --git a/Documentation/devicetree/bindings/misc/renesas,rcar-rst.txt b/Documentation/devicetree/bindings/misc/renesas,rcar-rst.txt new file mode 100644 index 0000000..88695c4 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/renesas,rcar-rst.txt @@ -0,0 +1,15 @@ +Renesas RCar r8a779x reset module +----------------------------------------------------- +This binding defines the reset module found on Renesas RCar r8a779x +SoCs. The reset module contains several reset related registers, +the meaning of them is implementation dependent. + +Required properties: +- compatible : "renesas,rcar-rst" +- reg : Location and size of the reset module + +Example: + reset-controller@e6160000 { + compatible = "renesas,rcar-rst"; + reg = <0 0xe6160000 0 0x200>; + }; \ No newline at end of file diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 83cf23c..d9b86c4 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1102,6 +1102,11 @@ #power-domain-cells = <0>; }; + reset-controller@e6160000 { + compatible = "renesas,rcar-rst"; + reg = <0 0xe6160000 0 0x200>; + }; + /* Variable factor clocks */ sd2_clk: sd2@e6150078 { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index db67e34..9c7a210 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1122,6 +1122,11 @@ #power-domain-cells = <0>; }; + reset-controller@e6160000 { + compatible = "renesas,rcar-rst"; + reg = <0 0xe6160000 0 0x200>; + }; + /* Variable factor clocks */ sd2_clk: sd2@e6150078 { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 1dd6d20..31858c6 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -933,6 +933,11 @@ #power-domain-cells = <0>; }; + reset-controller@e6160000 { + compatible = "renesas,rcar-rst"; + reg = <0 0xe6160000 0 0x200>; + }; + /* Variable factor clocks */ sd2_clk: sd2@e6150078 { compatible = "renesas,r8a7793-div6-clock", diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index f334a3a..c419ca6 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -932,6 +932,12 @@ "rcan"; #power-domain-cells = <0>; }; + + reset-controller@e6160000 { + compatible = "renesas,rcar-rst"; + reg = <0 0xe6160000 0 0x200>; + }; + /* Variable factor clocks */ sd2_clk: sd2@e6150078 { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 7181db0..1266975 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -309,6 +309,11 @@ #power-domain-cells = <0>; }; + reset-controller@e6160000 { + compatible = "renesas,rcar-rst"; + reg = <0 0xe6160000 0 0x200>; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a7795-sysc"; reg = <0 0xe6180000 0 0x0400>; diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 1389528..c3d6075 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -109,6 +109,11 @@ #power-domain-cells = <0>; }; + reset-controller@e6160000 { + compatible = "renesas,rcar-rst"; + reg = <0 0xe6160000 0 0x200>; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a7796-sysc"; reg = <0 0xe6180000 0 0x0400>;