| Message ID | 1513350890-2446-5-git-send-email-ulrich.hecht+renesas@gmail.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Simon Horman |
| Headers | show |
Hi Uli, On Fri, Dec 15, 2017 at 4:14 PM, Ulrich Hecht <ulrich.hecht+renesas@gmail.com> wrote: > From: Gaku Inami <gaku.inami.xw@bp.renesas.com> > > This patch supports GSX frequency scaling using devfreq. > > Includes update of the OPP tables for GSX because the typical voltage of > VDD_DVFS (power optimized) was updated to 0.83V by R-Car Gen3 EC Rev0.54E > specification. > > Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > Signed-off-by: Hien Dang <hien.dang.eb@renesas.com> > Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi > @@ -166,6 +166,27 @@ > }; > }; > > + gsx_opp_table: gsx_opp_table { > + compatible = "operating-points-v2"; > + > + opp@200000000 { opp-200000000 (try "make dtbs W=1") > + opp-hz = /bits/ 64 <200000000>; > + opp-microvolt = <830000>; > + }; > + opp@300000000 { > + opp-hz = /bits/ 64 <300000000>; > + opp-microvolt = <830000>; > + }; > + opp@400000000 { > + opp-hz = /bits/ 64 <400000000>; > + opp-microvolt = <830000>; > + }; > + opp@600000000 { > + opp-hz = /bits/ 64 <600000000>; > + opp-microvolt = <830000>; Do they really all use the same voltage? And AFAIU, DVFS is shared between CPU and GPU. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert-san, Ulrich-san, > Do they really all use the same voltage? > > And AFAIU, DVFS is shared between CPU and GPU. We support the opp table of GPU with the same voltage for each in R-Car H3/M3. As you know, DVFS is shared between CA57 and GPU. We understand that arbitration control of the voltage from both cores can't be realized with the current CPUFREQ and DEVFREQ framework. Therefore, we have implemented as above now. In our test with GPU team, it is fine except power consumption. Regards, Inami -----Original Message----- From: geert.uytterhoeven@gmail.com [mailto:geert.uytterhoeven@gmail.com] On Behalf Of Geert Uytterhoeven Sent: Monday, December 18, 2017 7:27 PM To: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Cc: Linux-Renesas <linux-renesas-soc@vger.kernel.org>; Laurent Pinchart <laurent.pinchart@ideasonboard.com>; Magnus Damm <magnus.damm@gmail.com>; Gaku Inami <gaku.inami.xw@bp.renesas.com>; TAKESHI KIHARA <takeshi.kihara.df@renesas.com>; Hien Dang <hien.dang.eb@renesas.com> Subject: Re: [PATCH 4/4] arm64: dts: r8a7796: Add DEVFREQ support for GSX Hi Uli, On Fri, Dec 15, 2017 at 4:14 PM, Ulrich Hecht <ulrich.hecht+renesas@gmail.com> wrote: > From: Gaku Inami <gaku.inami.xw@bp.renesas.com> > > This patch supports GSX frequency scaling using devfreq. > > Includes update of the OPP tables for GSX because the typical voltage > of VDD_DVFS (power optimized) was updated to 0.83V by R-Car Gen3 EC > Rev0.54E specification. > > Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > Signed-off-by: Hien Dang <hien.dang.eb@renesas.com> > Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi > @@ -166,6 +166,27 @@ > }; > }; > > + gsx_opp_table: gsx_opp_table { > + compatible = "operating-points-v2"; > + > + opp@200000000 { opp-200000000 (try "make dtbs W=1") > + opp-hz = /bits/ 64 <200000000>; > + opp-microvolt = <830000>; > + }; > + opp@300000000 { > + opp-hz = /bits/ 64 <300000000>; > + opp-microvolt = <830000>; > + }; > + opp@400000000 { > + opp-hz = /bits/ 64 <400000000>; > + opp-microvolt = <830000>; > + }; > + opp@600000000 { > + opp-hz = /bits/ 64 <600000000>; > + opp-microvolt = <830000>; Do they really all use the same voltage? And AFAIU, DVFS is shared between CPU and GPU. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index d3264e7..fb30390 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -166,6 +166,27 @@ }; }; + gsx_opp_table: gsx_opp_table { + compatible = "operating-points-v2"; + + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <830000>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <830000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <830000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <830000>; + }; + }; + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; @@ -2246,6 +2267,7 @@ reg = <0 0xfd000000 0 0x3ffff>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 112>; + operating-points-v2 = <&gsx_opp_table>; power-domains = <&sysc R8A7796_PD_3DG_B>; };