From patchwork Wed Mar 28 19:26:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 10313947 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7AE9260212 for ; Wed, 28 Mar 2018 19:30:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6BB18295FF for ; Wed, 28 Mar 2018 19:30:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 566BC29736; Wed, 28 Mar 2018 19:30:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A8AEF295FF for ; Wed, 28 Mar 2018 19:30:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752308AbeC1TaD (ORCPT ); Wed, 28 Mar 2018 15:30:03 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:50057 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752732AbeC1TaC (ORCPT ); Wed, 28 Mar 2018 15:30:02 -0400 Received: from unknown (HELO relmlir1.idc.renesas.com) ([10.200.68.151]) by relmlie2.idc.renesas.com with ESMTP; 29 Mar 2018 04:30:01 +0900 Received: from relmlii2.idc.renesas.com (relmlii2.idc.renesas.com [10.200.68.66]) by relmlir1.idc.renesas.com (Postfix) with ESMTP id 3F53060A9E; Thu, 29 Mar 2018 04:30:01 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.48,372,1517842800"; d="scan'208";a="276535428" Received: from unknown (HELO be1yocto.ree.adwin.renesas.com) ([172.29.43.62]) by relmlii2.idc.renesas.com with ESMTP; 29 Mar 2018 04:29:58 +0900 From: Biju Das To: Rob Herring , Mark Rutland Cc: Biju Das , Fabrizio Castro , devicetree@vger.kernel.org, Simon Horman , Geert Uytterhoeven , Chris Paterson , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 3/8] clk: renesas: Add r8a77470 CPG Core Clock Definitions Date: Wed, 28 Mar 2018 20:26:11 +0100 Message-Id: <1522265176-33226-4-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522265176-33226-1-git-send-email-biju.das@bp.renesas.com> References: <1522265176-33226-1-git-send-email-biju.das@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add all RZ/G1C Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2 ("List of Clocks [RZ/G1C]") of the RZ/G1C Hardware User's Manual. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven --- V1->V2: * incorporated geert's review comment include/dt-bindings/clock/r8a77470-cpg-mssr.h | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 include/dt-bindings/clock/r8a77470-cpg-mssr.h diff --git a/include/dt-bindings/clock/r8a77470-cpg-mssr.h b/include/dt-bindings/clock/r8a77470-cpg-mssr.h new file mode 100644 index 0000000..ffc123c --- /dev/null +++ b/include/dt-bindings/clock/r8a77470-cpg-mssr.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ + +#include + +/* r8a77470 CPG Core Clocks */ +#define R8A77470_CLK_Z2 0 +#define R8A77470_CLK_ZTR 2 +#define R8A77470_CLK_ZTRD2 3 +#define R8A77470_CLK_ZT 4 +#define R8A77470_CLK_ZX 5 +#define R8A77470_CLK_ZS 6 +#define R8A77470_CLK_HP 7 +#define R8A77470_CLK_B 9 +#define R8A77470_CLK_LB 10 +#define R8A77470_CLK_P 11 +#define R8A77470_CLK_CL 12 +#define R8A77470_CLK_CP 13 +#define R8A77470_CLK_M2 14 +#define R8A77470_CLK_ZB3 16 +#define R8A77470_CLK_SDH 19 +#define R8A77470_CLK_SD0 20 +#define R8A77470_CLK_SD1 21 +#define R8A77470_CLK_SD2 22 +#define R8A77470_CLK_MP 24 +#define R8A77470_CLK_QSPI 25 +#define R8A77470_CLK_CPEX 26 +#define R8A77470_CLK_RCAN 27 +#define R8A77470_CLK_R 28 +#define R8A77470_CLK_OSC 29 + +#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */