| Message ID | 1524238029-55315-4-git-send-email-biju.das@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Simon Horman |
| Headers | show |
On Fri, Apr 20, 2018 at 04:27:08PM +0100, Biju Das wrote: > Describe SCIF ports in the R8A77470 device tree. > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > --- > arch/arm/boot/dts/r8a77470.dtsi | 69 +++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 67 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi > index 2f89f33..39549f2 100644 > --- a/arch/arm/boot/dts/r8a77470.dtsi > +++ b/arch/arm/boot/dts/r8a77470.dtsi > @@ -190,19 +190,84 @@ > dma-channels = <15>; > }; > > + scif0: serial@e6e60000 { > + compatible = "renesas,scif-r8a77470", > + "renesas,rcar-gen2-scif", "renesas,scif"; > + reg = <0 0xe6e60000 0 0x40>; > + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 721>, > + <&cpg CPG_CORE 5>, <&scif_clk>; > + clock-names = "fck", "brg_int", "scif_clk"; > + power-domains = <&sysc 32>; > + resets = <&cpg 721>; > + status = "disabled"; > + }; > + > scif1: serial@e6e68000 { > compatible = "renesas,scif-r8a77470", > "renesas,rcar-gen2-scif", "renesas,scif"; > reg = <0 0xe6e68000 0 0x40>; > interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&cpg CPG_MOD 720>, > - <&cpg CPG_CORE 6>, <&scif_clk>; > + clocks = <&cpg CPG_MOD 720>, > + <&cpg CPG_CORE 5>, <&scif_clk>; I am a little unclear why the CPG clock is changed from 6 (ZS?) to 5 (ZX?). Could you clarify this for me? > clock-names = "fck", "brg_int", "scif_clk"; > power-domains = <&sysc 32>; > resets = <&cpg 720>; > status = "disabled"; > }; > > + scif2: serial@e6e58000 { > + compatible = "renesas,scif-r8a77470", > + "renesas,rcar-gen2-scif", "renesas,scif"; > + reg = <0 0xe6e58000 0 0x40>; > + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 719>, > + <&cpg CPG_CORE 5>, <&scif_clk>; > + clock-names = "fck", "brg_int", "scif_clk"; > + power-domains = <&sysc 32>; > + resets = <&cpg 719>; > + status = "disabled"; > + }; > + > + scif3: serial@e6ea8000 { > + compatible = "renesas,scif-r8a77470", > + "renesas,rcar-gen2-scif", "renesas,scif"; > + reg = <0 0xe6ea8000 0 0x40>; > + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 718>, > + <&cpg CPG_CORE 5>, <&scif_clk>; > + clock-names = "fck", "brg_int", "scif_clk"; > + power-domains = <&sysc 32>; > + resets = <&cpg 718>; > + status = "disabled"; > + }; > + > + scif4: serial@e6ee0000 { > + compatible = "renesas,scif-r8a77470", > + "renesas,rcar-gen2-scif", "renesas,scif"; > + reg = <0 0xe6ee0000 0 0x40>; > + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 715>, > + <&cpg CPG_CORE 5>, <&scif_clk>; > + clock-names = "fck", "brg_int", "scif_clk"; > + power-domains = <&sysc 32>; > + resets = <&cpg 715>; > + status = "disabled"; > + }; > + > + scif5: serial@e6ee8000 { > + compatible = "renesas,scif-r8a77470", > + "renesas,rcar-gen2-scif", "renesas,scif"; > + reg = <0 0xe6ee8000 0 0x40>; > + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 714>, > + <&cpg CPG_CORE 5>, <&scif_clk>; > + clock-names = "fck", "brg_int", "scif_clk"; > + power-domains = <&sysc 32>; > + resets = <&cpg 714>; > + status = "disabled"; > + }; > + > gic: interrupt-controller@f1001000 { > compatible = "arm,gic-400"; > #interrupt-cells = <3>; > -- > 2.7.4 >
Hi Simon, On Tue, Apr 24, 2018 at 9:08 AM, Simon Horman <horms@verge.net.au> wrote: > On Fri, Apr 20, 2018 at 04:27:08PM +0100, Biju Das wrote: >> Describe SCIF ports in the R8A77470 device tree. >> >> Signed-off-by: Biju Das <biju.das@bp.renesas.com> >> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> >> --- >> arch/arm/boot/dts/r8a77470.dtsi | 69 +++++++++++++++++++++++++++++++++++++++-- >> 1 file changed, 67 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi >> index 2f89f33..39549f2 100644 >> --- a/arch/arm/boot/dts/r8a77470.dtsi >> +++ b/arch/arm/boot/dts/r8a77470.dtsi >> @@ -190,19 +190,84 @@ >> dma-channels = <15>; >> }; >> >> + scif0: serial@e6e60000 { >> + compatible = "renesas,scif-r8a77470", >> + "renesas,rcar-gen2-scif", "renesas,scif"; >> + reg = <0 0xe6e60000 0 0x40>; >> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&cpg CPG_MOD 721>, >> + <&cpg CPG_CORE 5>, <&scif_clk>; >> + clock-names = "fck", "brg_int", "scif_clk"; >> + power-domains = <&sysc 32>; >> + resets = <&cpg 721>; >> + status = "disabled"; >> + }; >> + >> scif1: serial@e6e68000 { >> compatible = "renesas,scif-r8a77470", >> "renesas,rcar-gen2-scif", "renesas,scif"; >> reg = <0 0xe6e68000 0 0x40>; >> interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&cpg CPG_MOD 720>, >> - <&cpg CPG_CORE 6>, <&scif_clk>; >> + clocks = <&cpg CPG_MOD 720>, >> + <&cpg CPG_CORE 5>, <&scif_clk>; > > I am a little unclear why the CPG clock is changed from 6 (ZS?) to 5 (ZX?). > Could you clarify this for me? #define R8A77470_CLK_ZS 5 I guess you queued up the initial .dtsi before the error in include/dt-bindings/clock/r8a77470-cpg-mssr.h was detected? Gr{oetje,eeting}s, Geert
On Tue, Apr 24, 2018 at 09:19:39AM +0200, Geert Uytterhoeven wrote: > Hi Simon, > > On Tue, Apr 24, 2018 at 9:08 AM, Simon Horman <horms@verge.net.au> wrote: > > On Fri, Apr 20, 2018 at 04:27:08PM +0100, Biju Das wrote: > >> Describe SCIF ports in the R8A77470 device tree. > >> > >> Signed-off-by: Biju Das <biju.das@bp.renesas.com> > >> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > >> --- > >> arch/arm/boot/dts/r8a77470.dtsi | 69 +++++++++++++++++++++++++++++++++++++++-- > >> 1 file changed, 67 insertions(+), 2 deletions(-) > >> > >> diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi > >> index 2f89f33..39549f2 100644 > >> --- a/arch/arm/boot/dts/r8a77470.dtsi > >> +++ b/arch/arm/boot/dts/r8a77470.dtsi > >> @@ -190,19 +190,84 @@ > >> dma-channels = <15>; > >> }; > >> > >> + scif0: serial@e6e60000 { > >> + compatible = "renesas,scif-r8a77470", > >> + "renesas,rcar-gen2-scif", "renesas,scif"; > >> + reg = <0 0xe6e60000 0 0x40>; > >> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; > >> + clocks = <&cpg CPG_MOD 721>, > >> + <&cpg CPG_CORE 5>, <&scif_clk>; > >> + clock-names = "fck", "brg_int", "scif_clk"; > >> + power-domains = <&sysc 32>; > >> + resets = <&cpg 721>; > >> + status = "disabled"; > >> + }; > >> + > >> scif1: serial@e6e68000 { > >> compatible = "renesas,scif-r8a77470", > >> "renesas,rcar-gen2-scif", "renesas,scif"; > >> reg = <0 0xe6e68000 0 0x40>; > >> interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; > >> - clocks = <&cpg CPG_MOD 720>, > >> - <&cpg CPG_CORE 6>, <&scif_clk>; > >> + clocks = <&cpg CPG_MOD 720>, > >> + <&cpg CPG_CORE 5>, <&scif_clk>; > > > > I am a little unclear why the CPG clock is changed from 6 (ZS?) to 5 (ZX?). > > Could you clarify this for me? > > #define R8A77470_CLK_ZS 5 > > I guess you queued up the initial .dtsi before the error in > include/dt-bindings/clock/r8a77470-cpg-mssr.h was detected? Thanks, I see that ZS is 5 in renesas-drivers, but when looking at an earlier version of the patch to add the indexes it was 6. I think that explains things. But could we add an explanation to the changelog?
Hi Simon and Geert, Thanks for the feedback. > Subject: Re: [PATCH 3/4] ARM: dts: r8a77470: Add SCIF support > > On Tue, Apr 24, 2018 at 09:19:39AM +0200, Geert Uytterhoeven wrote: > > Hi Simon, > > > > On Tue, Apr 24, 2018 at 9:08 AM, Simon Horman <horms@verge.net.au> > wrote: > > > On Fri, Apr 20, 2018 at 04:27:08PM +0100, Biju Das wrote: > > >> Describe SCIF ports in the R8A77470 device tree. > > >> > > >> Signed-off-by: Biju Das <biju.das@bp.renesas.com> > > >> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > >> --- > > >> arch/arm/boot/dts/r8a77470.dtsi | 69 > > >> +++++++++++++++++++++++++++++++++++++++-- > > >> 1 file changed, 67 insertions(+), 2 deletions(-) > > >> > > >> diff --git a/arch/arm/boot/dts/r8a77470.dtsi > > >> b/arch/arm/boot/dts/r8a77470.dtsi index 2f89f33..39549f2 100644 > > >> --- a/arch/arm/boot/dts/r8a77470.dtsi > > >> +++ b/arch/arm/boot/dts/r8a77470.dtsi > > >> @@ -190,19 +190,84 @@ > > >> dma-channels = <15>; > > >> }; > > >> > > >> + scif0: serial@e6e60000 { > > >> + compatible = "renesas,scif-r8a77470", > > >> + "renesas,rcar-gen2-scif", "renesas,scif"; > > >> + reg = <0 0xe6e60000 0 0x40>; > > >> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; > > >> + clocks = <&cpg CPG_MOD 721>, > > >> + <&cpg CPG_CORE 5>, <&scif_clk>; > > >> + clock-names = "fck", "brg_int", "scif_clk"; > > >> + power-domains = <&sysc 32>; > > >> + resets = <&cpg 721>; > > >> + status = "disabled"; > > >> + }; > > >> + > > >> scif1: serial@e6e68000 { > > >> compatible = "renesas,scif-r8a77470", > > >> "renesas,rcar-gen2-scif", "renesas,scif"; > > >> reg = <0 0xe6e68000 0 0x40>; > > >> interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; > > >> - clocks = <&cpg CPG_MOD 720>, > > >> - <&cpg CPG_CORE 6>, <&scif_clk>; > > >> + clocks = <&cpg CPG_MOD 720>, > > >> + <&cpg CPG_CORE 5>, <&scif_clk>; > > > > > > I am a little unclear why the CPG clock is changed from 6 (ZS?) to 5 (ZX?). > > > Could you clarify this for me? > > > > #define R8A77470_CLK_ZS 5 > > > > I guess you queued up the initial .dtsi before the error in > > include/dt-bindings/clock/r8a77470-cpg-mssr.h was detected? > > Thanks, I see that ZS is 5 in renesas-drivers, but when looking at an earlier > version of the patch to add the indexes it was 6. Yes, I took this value from renesas-drivers. > I think that explains things. But could we add an explanation to the > changelog? OK. I will add the explanation to the change log. Regards, Biju Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 2f89f33..39549f2 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -190,19 +190,84 @@ dma-channels = <15>; }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE 5>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc 32>; + resets = <&cpg 721>; + status = "disabled"; + }; + scif1: serial@e6e68000 { compatible = "renesas,scif-r8a77470", "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e68000 0 0x40>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE 6>, <&scif_clk>; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE 5>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&sysc 32>; resets = <&cpg 720>; status = "disabled"; }; + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE 5>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc 32>; + resets = <&cpg 719>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE 5>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc 32>; + resets = <&cpg 718>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 715>, + <&cpg CPG_CORE 5>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc 32>; + resets = <&cpg 715>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>, + <&cpg CPG_CORE 5>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc 32>; + resets = <&cpg 714>; + status = "disabled"; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;