From patchwork Mon Jun 4 17:49:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Kaneko X-Patchwork-Id: 10447085 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3D27E60375 for ; Mon, 4 Jun 2018 17:49:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2ADA228D28 for ; Mon, 4 Jun 2018 17:49:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1F63A28D31; Mon, 4 Jun 2018 17:49:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 99D7928D28 for ; Mon, 4 Jun 2018 17:49:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751366AbeFDRtf (ORCPT ); Mon, 4 Jun 2018 13:49:35 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:39359 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750985AbeFDRtb (ORCPT ); Mon, 4 Jun 2018 13:49:31 -0400 Received: by mail-pg0-f65.google.com with SMTP id w12-v6so13551822pgc.6 for ; Mon, 04 Jun 2018 10:49:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=B3BgTdWMtRtfiycXPOzmcCfNmybtJ39ZM0vRvrCGaZg=; b=ePUsOzKpwvUzZJc4qXitmfYj3hsEEQE+twIeTnWRXqU3iBrbFWJ0kp7/ICkeBwM3yG TPBVAXLeCnvZvefi8cFU9JKE1/rXAthNYSEgAoSnc09Au0kIkulm5aOWwBuFUJQEBYjo QScD+0G4m/CHzn/+zBRm94ei1Wt9iBvKxetC2g2lugfWfhPgAUeJB2qE9OHswi/IVAUr Nb8sQqlb5kEx0krQUi4sNXvu3Rgpo4nVTQHtj0X6TOneQ32qtXurHr+Se6t1wDQ7P9bd IilCV8fi1OSr2IuG8DaSh08ap6XfZrU1HYMW1Q0Os2GUCnLOAlRwjzoLU+yovAg1lyvw 1hpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=B3BgTdWMtRtfiycXPOzmcCfNmybtJ39ZM0vRvrCGaZg=; b=iyH68VrnFBpjDeSmhfNML+OEnuUn1p+m6XuYQD/KdnQTOhjkG3DtWBR36j9HXP9aOc tqUZN6uRA7NrQFA4UOOS39wLYNB2t0Vrg3TfeeMjtn4rtFzsP64W5mt5VVosWnTSmveH v5k473jYSodjGhDxdTe/+gC83l+R9WucIqhnlwG2KV97Lbr737/J2kCOZng/a/mArR2b BwDPjGQVy/hMFKqBeXs5RssVCxinDwpgG+vMhHbSmqvdTmltT2nLxch2yRnP/KmgCosO gw1y46as7aKCrScS+IGDnMvRZd4F4/nzULXKYyontoOpYV0MGSGTNwMSzINJr3Hw6zBF xILw== X-Gm-Message-State: ALKqPwcPJ1JzUREDBHtqOhSqCleS4ZL1xPUovpib1Z8/twepVniDQYgk VgOVZpyPsdJvn8KeQbEuElHprQ== X-Google-Smtp-Source: ADUXVKL+1fCNejaRVgmchDFaNgIiA7YWszGlhcUdqCaAdnnqmi8dKeRJsinTniq6090qqkyBn3MwXw== X-Received: by 2002:a62:3889:: with SMTP id f131-v6mr22281075pfa.173.1528134571010; Mon, 04 Jun 2018 10:49:31 -0700 (PDT) Received: from localhost.localdomain (KD118155013174.ppp-bb.dion.ne.jp. [118.155.13.174]) by smtp.gmail.com with ESMTPSA id 82-v6sm31559489pft.74.2018.06.04.10.49.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 04 Jun 2018 10:49:30 -0700 (PDT) From: Yoshihiro Kaneko To: linux-renesas-soc@vger.kernel.org Cc: Simon Horman , Magnus Damm , linux-arm-kernel@lists.infradead.org Subject: [PATCH] arm64: dts: renesas: r8a7796: Add PCIe device nodes Date: Tue, 5 Jun 2018 02:49:08 +0900 Message-Id: <1528134548-17492-1-git-send-email-ykaneko0929@gmail.com> X-Mailer: git-send-email 1.9.1 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Harunobu Kurokawa This patch adds PCIe{0,1} device nodes for R8A7796 SoC. Signed-off-by: Harunobu Kurokawa Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko Reviewed-by: Simon Horman --- This patch is based on the devel branch of Simon Horman's renesas tree. arch/arm64/boot/dts/renesas/r8a7796.dtsi | 50 ++++++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 7c25be6..2a04635b 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for the r8a7796 SoC * - * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2016-2017 Renesas Electronics Corp. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -2108,13 +2108,57 @@ }; pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a7796", + "renesas,pcie-rcar-gen3"; reg = <0 0xfe000000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; }; pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a7796", + "renesas,pcie-rcar-gen3"; reg = <0 0xee800000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; }; imr-lx4@fe860000 {