| Message ID | 1533219087-33695-4-git-send-email-biju.das@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Simon Horman |
| Headers | show |
| Series | Add GPIO and EAVB Pinctrl support | expand |
Hi Biju, On Thu, Aug 2, 2018 at 4:17 PM Biju Das <biju.das@bp.renesas.com> wrote: > Describe GPIO blocks in the R8A77470 device tree. > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Thanks for your patch! Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- a/arch/arm/boot/dts/r8a77470.dtsi > +++ b/arch/arm/boot/dts/r8a77470.dtsi > + gpio3: gpio@e6053000 { > + compatible = "renesas,gpio-r8a77470", > + "renesas,rcar-gen2-gpio"; > + reg = <0 0xe6053000 0 0x50>; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-reserved-ranges = <17 10>; > + gpio-ranges = <&pfc 0 96 30>; I would reverse the order of these two properties, but that's purely cosmetic. Gr{oetje,eeting}s, Geert
Hi Geert, Thanks for the feedback. > -----Original Message----- > From: devicetree-owner@vger.kernel.org <devicetree- > owner@vger.kernel.org> On Behalf Of Geert Uytterhoeven > Sent: 03 August 2018 10:10 > To: Biju Das <biju.das@bp.renesas.com> > Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland > <mark.rutland@arm.com>; Simon Horman <horms@verge.net.au>; Magnus > Damm <magnus.damm@gmail.com>; Linux-Renesas <linux-renesas- > soc@vger.kernel.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE > TREE BINDINGS <devicetree@vger.kernel.org>; Geert Uytterhoeven > <geert+renesas@glider.be>; Chris Paterson > <Chris.Paterson2@renesas.com>; Fabrizio Castro > <fabrizio.castro@bp.renesas.com> > Subject: Re: [PATCH v2 3/5] ARM: dts: r8a77470: Add GPIO support > > Hi Biju, > > On Thu, Aug 2, 2018 at 4:17 PM Biju Das <biju.das@bp.renesas.com> wrote: > > Describe GPIO blocks in the R8A77470 device tree. > > > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > Thanks for your patch! > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > --- a/arch/arm/boot/dts/r8a77470.dtsi > > +++ b/arch/arm/boot/dts/r8a77470.dtsi > > > + gpio3: gpio@e6053000 { > > + compatible = "renesas,gpio-r8a77470", > > + "renesas,rcar-gen2-gpio"; > > + reg = <0 0xe6053000 0 0x50>; > > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > > + #gpio-cells = <2>; > > + gpio-controller; > > + gpio-reserved-ranges = <17 10>; > > + gpio-ranges = <&pfc 0 96 30>; > > I would reverse the order of these two properties, but that's purely > cosmetic. Will send V3 with this change. Regards, Biju Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index af65fa0..5af878b 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -61,6 +61,97 @@ #size-cells = <2>; ranges; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 23>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 23>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-reserved-ranges = <17 10>; + gpio-ranges = <&pfc 0 96 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a77470"; reg = <0 0xe6060000 0 0x118>;