| Message ID | 1554443049-25127-2-git-send-email-cv-dong@jinso.co.jp (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 720066d17c973fd8721b326793add4430631c82b |
| Delegated to: | Simon Horman |
| Headers | show |
| Series | Add CMT support for R-Car H3/M3-N/E3 | expand |
On Fri, Apr 05, 2019 at 02:44:06PM +0900, Cao Van Dong wrote: > This patch adds CMT{0|1|2|3} device nodes for r8a7795 SoC. > > Tested-by: Cao Van Dong <cv-dong@jinso.co.jp> > Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Thanks, This looks fine to me but I will wait to see if there are other reviews before applying. Reviewed-by: Simon Horman <horms+renesas@verge.net.au> I am, however, curious to know how you tested this. Likewise for patches 2/4 and 3/4.
Dear Simon-san, On 2019/04/05 17:17, Simon Horman wrote: > On Fri, Apr 05, 2019 at 02:44:06PM +0900, Cao Van Dong wrote: >> This patch adds CMT{0|1|2|3} device nodes for r8a7795 SoC. >> >> Tested-by: Cao Van Dong <cv-dong@jinso.co.jp> >> Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> > Thanks, > > This looks fine to me but I will wait to see if there are other reviews > before applying. > > Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Thanks you for review! > I am, however, curious to know how you tested this. > > Likewise for patches 2/4 and 3/4. Always thanks for your curious! After booting, I checked the existence of the device and the device interrupt. Thanks you, Dong
On Fri, Apr 05, 2019 at 06:02:30PM +0900, Cao Van Dong wrote: > Dear Simon-san, > > On 2019/04/05 17:17, Simon Horman wrote: > > On Fri, Apr 05, 2019 at 02:44:06PM +0900, Cao Van Dong wrote: > > > This patch adds CMT{0|1|2|3} device nodes for r8a7795 SoC. > > > > > > Tested-by: Cao Van Dong <cv-dong@jinso.co.jp> > > > Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> > > Thanks, > > > > This looks fine to me but I will wait to see if there are other reviews > > before applying. > > > > Reviewed-by: Simon Horman <horms+renesas@verge.net.au> > Thanks you for review! > > I am, however, curious to know how you tested this. > > > > Likewise for patches 2/4 and 3/4. > Always thanks for your curious! > After booting, I checked the existence of the device and the device > interrupt. Thanks, I have applied patches 1/4, 2/4 and 3/4 for inclusion in v5.2.
On Fri, Apr 5, 2019 at 7:44 AM Cao Van Dong <cv-dong@jinso.co.jp> wrote: > This patch adds CMT{0|1|2|3} device nodes for r8a7795 SoC. > > Tested-by: Cao Van Dong <cv-dong@jinso.co.jp> > Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 55472b2..097538c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -462,6 +462,76 @@ reg = <0 0xe6060000 0 0x50c>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a7795-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7795-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a7795-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a7795-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7795-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>;
This patch adds CMT{0|1|2|3} device nodes for r8a7795 SoC. Tested-by: Cao Van Dong <cv-dong@jinso.co.jp> Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 70 ++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+)