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[118.155.13.174]) by smtp.gmail.com with ESMTPSA id v44sm8653934pgn.17.2019.09.26.13.00.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Sep 2019 13:00:06 -0700 (PDT) From: Yoshihiro Kaneko To: linux-renesas-soc@vger.kernel.org Cc: Rob Herring , Geert Uytterhoeven , Simon Horman , Magnus Damm , devicetree@vger.kernel.org Subject: [PATCH v2] dt-bindings: irqchip: renesas: intc-irqpin: convert bindings to json-schema Date: Fri, 27 Sep 2019 04:59:37 +0900 Message-Id: <1569527977-21213-1-git-send-email-ykaneko0929@gmail.com> X-Mailer: git-send-email 1.9.1 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Convert R-/SH-Mobile IRQPin Controller bindings documentation to json-schema. Signed-off-by: Yoshihiro Kaneko --- v2 - correct Geert-san's E-mail address. - delete Guennadi-san from the maintainer of this binding. - give 'sense-bitfield-width' the uint32 type. - describe 'control-parent' property as a boolean. .../interrupt-controller/renesas,intc-irqpin.txt | 62 ------------- .../interrupt-controller/renesas,intc-irqpin.yaml | 102 +++++++++++++++++++++ 2 files changed, 102 insertions(+), 62 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt deleted file mode 100644 index 772c550..0000000 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt +++ /dev/null @@ -1,62 +0,0 @@ -DT bindings for the R-/SH-Mobile irqpin controller - -Required properties: - -- compatible: has to be "renesas,intc-irqpin-", "renesas,intc-irqpin" - as fallback. - Examples with soctypes are: - - "renesas,intc-irqpin-r8a7740" (R-Mobile A1) - - "renesas,intc-irqpin-r8a7778" (R-Car M1A) - - "renesas,intc-irqpin-r8a7779" (R-Car H1) - - "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5) - -- reg: Base address and length of each register bank used by the external - IRQ pins driven by the interrupt controller hardware module. The base - addresses, length and number of required register banks varies with soctype. -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in - interrupts.txt in this directory. -- interrupts: Must contain a list of interrupt specifiers. For each interrupt - provided by this irqpin controller instance, there must be one entry, - referring to the corresponding parent interrupt. - -Optional properties: - -- any properties, listed in interrupts.txt, and any standard resource allocation - properties -- sense-bitfield-width: width of a single sense bitfield in the SENSE register, - if different from the default 4 bits -- control-parent: disable and enable interrupts on the parent interrupt - controller, needed for some broken implementations -- clocks: Must contain a reference to the functional clock. This property is - mandatory if the hardware implements a controllable functional clock for - the irqpin controller instance. -- power-domains: Must contain a reference to the power domain. This property is - mandatory if the irqpin controller instance is part of a controllable power - domain. - - -Example -------- - - irqpin1: interrupt-controller@e6900004 { - compatible = "renesas,intc-irqpin-r8a7740", - "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900004 4>, - <0xe6900014 4>, - <0xe6900024 1>, - <0xe6900044 1>, - <0xe6900064 1>; - interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7740_CLK_INTCA>; - power-domains = <&pd_a4s>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml new file mode 100644 index 0000000..5925890 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DT bindings for the R-/SH-Mobile irqpin controller + +maintainers: + - Geert Uytterhoeven + +properties: + compatible: + items: + - enum: + - renesas,intc-irqpin-r8a7740 # R-Mobile A1 + - renesas,intc-irqpin-r8a7778 # R-Car M1A + - renesas,intc-irqpin-r8a7779 # R-Car H1 + - renesas,intc-irqpin-sh73a0 # SH-Mobile AG5 + - const: renesas,intc-irqpin + + reg: + # Base address and length of each register bank used by the external + # IRQ pins driven by the interrupt controller hardware module. The base + # addresses, length and number of required register banks varies with + # soctype. + minItems: 1 + maxItems: 6 + + interrupt-controller: true + # Identifies the node as an interrupt controller. + + '#interrupt-cells': + # an interrupt index and flags, as defined in interrupts.txt in this + # directory. + const: 2 + + interrupts: + # Must contain a list of interrupt specifiers. For each interrupt + # provided by this irqpin controller instance, there must be one entry, + # referring to the corresponding parent interrupt. + maxItems: 1 + + sense-bitfield-width: + # width of a single sense bitfield in the SENSE register, if different + # from the default 4 bits + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + + control-parent: + # disable and enable interrupts on the parent interrupt controller, + # needed for some broken implementations + type: boolean + + clocks: + # Must contain a reference to the functional clock. This property is + # mandatory if the hardware implements a controllable functional clock for + # the irqpin controller instance. + maxItems: 1 + + power-domains: + # Must contain a reference to the power domain. This property is + # mandatory if the irqpin controller instance is part of a controllable + # power domain. + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + #include + + irqpin1: interrupt-controller@e6900004 { + compatible = "renesas,intc-irqpin-r8a7740", + "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900004 4>, + <0xe6900014 4>, + <0xe6900024 1>, + <0xe6900044 1>, + <0xe6900064 1>; + interrupts = ; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; + power-domains = <&pd_a4s>; + };