diff mbox series

[v2,09/10] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM

Message ID 1588542414-14826-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State Accepted
Delegated to: Geert Uytterhoeven
Headers show
Series Add initial support for R8A7742/RZG1H SoC and iW-RainboW-G21D-Qseven development board support | expand

Commit Message

Prabhakar May 3, 2020, 9:46 p.m. UTC 
Add support for iWave RZ/G1H Qseven System On Module.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
 arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 53 +++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 arch/arm/boot/dts/r8a7742-iwg21m.dtsi

Comments

Geert Uytterhoeven May 4, 2020, 1:01 p.m. UTC | #1 
Hi Prabhakar,

On Sun, May 3, 2020 at 11:48 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add support for iWave RZ/G1H Qseven System On Module.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the iWave RZ/G1H Qseven SOM
> + *
> + * Copyright (C) 2020 Renesas Electronics Corp.
> + */
> +
> +#include "r8a7742.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +       compatible = "iwave,g21m", "renesas,r8a7742";
> +
> +       memory@40000000 {
> +               device_type = "memory";
> +               reg = <0 0x40000000 0 0x40000000>;
> +       };
> +
> +       memory@200000000 {
> +               device_type = "memory";
> +               reg = <2 0x00000000 0 0x20000000>;

According to the schematics, the second bank is also 1 GiB, so the
reg length should be 0x40000000.

> +       };

> +&pfc {
> +       mmc1_pins: mmc1 {
> +               groups = "mmc1_data4", "mmc1_ctrl";
> +               function = "mmc1";
> +       };
> +};
> +
> +&mmcif1 {
> +       pinctrl-0 = <&mmc1_pins>;
> +       pinctrl-names = "default";
> +
> +       vmmc-supply = <&reg_3p3v>;
> +       bus-width = <4>;
> +       non-removable;
> +       status = "okay";
> +};

The eMMC has an 8-bit data path.  Is there any specific reason you use
bus-width = <4>, and the "mmc1_data4" pin group?

Gr{oetje,eeting}s,

                        Geert
Lad, Prabhakar May 4, 2020, 2:20 p.m. UTC | #2 
Hi Geert,

Thank you for the review.

On Mon, May 4, 2020 at 2:01 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Sun, May 3, 2020 at 11:48 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > Add support for iWave RZ/G1H Qseven System On Module.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
> > @@ -0,0 +1,53 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device Tree Source for the iWave RZ/G1H Qseven SOM
> > + *
> > + * Copyright (C) 2020 Renesas Electronics Corp.
> > + */
> > +
> > +#include "r8a7742.dtsi"
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> > +/ {
> > +       compatible = "iwave,g21m", "renesas,r8a7742";
> > +
> > +       memory@40000000 {
> > +               device_type = "memory";
> > +               reg = <0 0x40000000 0 0x40000000>;
> > +       };
> > +
> > +       memory@200000000 {
> > +               device_type = "memory";
> > +               reg = <2 0x00000000 0 0x20000000>;
>
> According to the schematics, the second bank is also 1 GiB, so the
> reg length should be 0x40000000.
>
Agreed will fix that.

> > +       };
>
> > +&pfc {
> > +       mmc1_pins: mmc1 {
> > +               groups = "mmc1_data4", "mmc1_ctrl";
> > +               function = "mmc1";
> > +       };
> > +};
> > +
> > +&mmcif1 {
> > +       pinctrl-0 = <&mmc1_pins>;
> > +       pinctrl-names = "default";
> > +
> > +       vmmc-supply = <&reg_3p3v>;
> > +       bus-width = <4>;
> > +       non-removable;
> > +       status = "okay";
> > +};
>
> The eMMC has an 8-bit data path.  Is there any specific reason you use
> bus-width = <4>, and the "mmc1_data4" pin group?
>
MMC1_DATA7 is shared with VI1_CLK, so instead of limiting to only one
device when using 8-bit just switched to 4bit mode so that both the
peripherals can be used.

Cheers,
--Prabhakar

> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
Geert Uytterhoeven May 4, 2020, 2:29 p.m. UTC | #3 
Hi Prabhakar,

On Mon, May 4, 2020 at 4:20 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Mon, May 4, 2020 at 2:01 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Sun, May 3, 2020 at 11:48 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > Add support for iWave RZ/G1H Qseven System On Module.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>

> > > --- /dev/null
> > > +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
> > > @@ -0,0 +1,53 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Device Tree Source for the iWave RZ/G1H Qseven SOM
> > > + *
> > > + * Copyright (C) 2020 Renesas Electronics Corp.
> > > + */
> > > +
> > > +#include "r8a7742.dtsi"
> > > +#include <dt-bindings/gpio/gpio.h>
> > > +
> > > +/ {
> > > +       compatible = "iwave,g21m", "renesas,r8a7742";
> > > +
> > > +       memory@40000000 {
> > > +               device_type = "memory";
> > > +               reg = <0 0x40000000 0 0x40000000>;
> > > +       };
> > > +
> > > +       memory@200000000 {
> > > +               device_type = "memory";
> > > +               reg = <2 0x00000000 0 0x20000000>;
> >
> > According to the schematics, the second bank is also 1 GiB, so the
> > reg length should be 0x40000000.
> >
> Agreed will fix that.

Thanks for the confirmation.  I can fix that while applying.

> > > +       };
> >
> > > +&pfc {
> > > +       mmc1_pins: mmc1 {
> > > +               groups = "mmc1_data4", "mmc1_ctrl";
> > > +               function = "mmc1";
> > > +       };
> > > +};
> > > +
> > > +&mmcif1 {
> > > +       pinctrl-0 = <&mmc1_pins>;
> > > +       pinctrl-names = "default";
> > > +
> > > +       vmmc-supply = <&reg_3p3v>;
> > > +       bus-width = <4>;
> > > +       non-removable;
> > > +       status = "okay";
> > > +};
> >
> > The eMMC has an 8-bit data path.  Is there any specific reason you use
> > bus-width = <4>, and the "mmc1_data4" pin group?
> >
> MMC1_DATA7 is shared with VI1_CLK, so instead of limiting to only one
> device when using 8-bit just switched to 4bit mode so that both the
> peripherals can be used.

OK.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.8 with the above fixed.

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
new file mode 100644
index 000000000000..3d22de47f337
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
@@ -0,0 +1,53 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave RZ/G1H Qseven SOM
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a7742.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "iwave,g21m", "renesas,r8a7742";
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0x40000000>;
+	};
+
+	memory@200000000 {
+		device_type = "memory";
+		reg = <2 0x00000000 0 0x20000000>;
+	};
+
+	reg_3p3v: 3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <20000000>;
+};
+
+&pfc {
+	mmc1_pins: mmc1 {
+		groups = "mmc1_data4", "mmc1_ctrl";
+		function = "mmc1";
+	};
+};
+
+&mmcif1 {
+	pinctrl-0 = <&mmc1_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&reg_3p3v>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};