From patchwork Fri Feb 12 19:05:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 8296051 Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3A443C02AA for ; Fri, 12 Feb 2016 19:07:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6E18420225 for ; Fri, 12 Feb 2016 19:07:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F1CFA20454 for ; Fri, 12 Feb 2016 19:07:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751031AbcBLTHh (ORCPT ); Fri, 12 Feb 2016 14:07:37 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:41775 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750961AbcBLTHh (ORCPT ); Fri, 12 Feb 2016 14:07:37 -0500 Received: from penelope.kanocho.kobe.vergenet.net (128-47-71-217.dyn.estpak.ee [217.71.47.128]) by kirsty.vergenet.net (Postfix) with ESMTPSA id 2B77025BEE8; Sat, 13 Feb 2016 06:06:48 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1455304008; bh=LKL0ULbWjziS4ro/AbbcJgZ3B9Nqa0Mlyqzw7tkxaHw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JmZq+Xu9/jCk9T0aluIRIb865XTKtBLYRRTKW9qFLHdLVdbkeXowytt9WtUykAGJA O/2oa9SNmi07jZinrhmOweCSxvL5U1+6Qxa4JgqTKZeC2nxaJBQhee7FNOiTv+uf41 7D6cwP4elujaQV3kyKiVb3t4WRFxTdOeWVX68IHM= Received: by penelope.kanocho.kobe.vergenet.net (Postfix, from userid 7100) id 3404261170; Sat, 13 Feb 2016 06:06:11 +1100 (AEDT) From: Simon Horman To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm , Geert Uytterhoeven , Simon Horman Subject: [PATCH 59/68] ARM: dts: r8a7793: Add BRG support for SCIF Date: Fri, 12 Feb 2016 20:05:49 +0100 Message-Id: <166d8ca693a9a1f4f3285ba03d9aebe7f679753f.1455303422.git.horms+renesas@verge.net.au> X-Mailer: git-send-email 2.7.0.rc3.207.g0ac5344 In-Reply-To: References: Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Geert Uytterhoeven Add the device node for the external SCIF_CLK. The presence of the SCIF_CLK crystal and its clock frequency depends on the actual board. Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal resp. external clock) for the Baud Rate Generator for External Clock (BRG) to all SCIF and HSCIF device nodes. This increases the range and accuracy of supported baud rates on (H)SCIF. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793.dtsi | 54 ++++++++++++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 07af584915c6..45dba1c79a43 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -600,8 +600,9 @@ "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF0>; - clock-names = "fck"; + clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; @@ -613,8 +614,9 @@ "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF1>; - clock-names = "fck"; + clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; @@ -626,8 +628,9 @@ "renesas,scif"; reg = <0 0xe6e58000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF2>; - clock-names = "fck"; + clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; @@ -639,8 +642,9 @@ "renesas,scif"; reg = <0 0xe6ea8000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF3>; - clock-names = "fck"; + clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; @@ -652,8 +656,9 @@ "renesas,scif"; reg = <0 0xe6ee0000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF4>; - clock-names = "fck"; + clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; @@ -665,8 +670,9 @@ "renesas,scif"; reg = <0 0xe6ee8000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF5>; - clock-names = "fck"; + clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; @@ -678,8 +684,9 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>; - clock-names = "fck"; + clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; @@ -691,8 +698,9 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>; - clock-names = "fck"; + clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; @@ -704,8 +712,9 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62d0000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>; - clock-names = "fck"; + clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; @@ -805,6 +814,15 @@ clock-output-names = "audio_clk_c"; }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7793-cpg-clocks",