From patchwork Mon Sep 12 14:15:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 9326603 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4DD3560839 for ; Mon, 12 Sep 2016 14:16:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 40839289E3 for ; Mon, 12 Sep 2016 14:16:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 352C028D87; Mon, 12 Sep 2016 14:16:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 92EFE289E3 for ; Mon, 12 Sep 2016 14:16:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933179AbcILOQD (ORCPT ); Mon, 12 Sep 2016 10:16:03 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:26827 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933171AbcILOQC (ORCPT ); Mon, 12 Sep 2016 10:16:02 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie2.idc.renesas.com with ESMTP; 12 Sep 2016 23:16:01 +0900 Received: from relmlac3.idc.renesas.com (relmlac3.idc.renesas.com [10.200.69.23]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id 46A8852BD1; Mon, 12 Sep 2016 23:16:01 +0900 (JST) Received: by relmlac3.idc.renesas.com (Postfix, from userid 0) id 4149A1800A; Mon, 12 Sep 2016 23:16:01 +0900 (JST) Received: from relmlac3.idc.renesas.com (localhost [127.0.0.1]) by relmlac3.idc.renesas.com (Postfix) with ESMTP id 3876E18077; Mon, 12 Sep 2016 23:16:01 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac3.idc.renesas.com with ESMTP id ZAD24109; Mon, 12 Sep 2016 23:16:01 +0900 X-IronPort-AV: E=Sophos;i="5.22,559,1449500400"; d="scan'208";a="219514671" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii1.idc.renesas.com with ESMTP; 12 Sep 2016 23:15:59 +0900 Received: from localhost.localdomain (unknown [143.103.58.245]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id 5F2D4454; Mon, 12 Sep 2016 14:15:58 +0000 (UTC) From: Chris Brandt To: Ulf Hansson , Wolfram Sang , Sergei Shtylyov , Geert Uytterhoeven Cc: Simon Horman , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Brandt Subject: [PATCH v3 2/3] mmc: tmio-mmc: add support for 32bit data port Date: Mon, 12 Sep 2016 10:15:06 -0400 Message-Id: <20160912141507.6837-3-chris.brandt@renesas.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20160912141507.6837-1-chris.brandt@renesas.com> References: <20160912141507.6837-1-chris.brandt@renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For the r7s72100 SOC, the DATA_PORT register was changed to 32-bits wide. Therefore a new flag has been created that will allow 32-bit reads/writes to the DATA_PORT register instead of 16-bit (because 16-bits accesses are not supported). Signed-off-by: Chris Brandt Reviewed-by: Wolfram Sang --- v3: * changed loops to memcpy v2: * changed 'data * 0xFF' to 'data & 0xFF' * added 'const' for sd_ctrl_write32_rep --- drivers/mmc/host/tmio_mmc.h | 12 ++++++++++++ drivers/mmc/host/tmio_mmc_pio.c | 30 ++++++++++++++++++++++++++++++ include/linux/mfd/tmio.h | 5 +++++ 3 files changed, 47 insertions(+) diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h index ecb99fc..a99e634 100644 --- a/drivers/mmc/host/tmio_mmc.h +++ b/drivers/mmc/host/tmio_mmc.h @@ -237,6 +237,12 @@ static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host, int ad readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16; } +static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr, + u32 *buf, int count) +{ + readsl(host->ctl + (addr << host->bus_shift), buf, count); +} + static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, u16 val) { /* If there is a hook and it returns non-zero then there @@ -259,4 +265,10 @@ static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host, int writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift)); } +static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr, + const u32 *buf, int count) +{ + writesl(host->ctl + (addr << host->bus_shift), buf, count); +} + #endif diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c index 017a4dc..59fac7d 100644 --- a/drivers/mmc/host/tmio_mmc_pio.c +++ b/drivers/mmc/host/tmio_mmc_pio.c @@ -443,6 +443,36 @@ static void tmio_mmc_transfer_data(struct tmio_mmc_host *host, /* * Transfer the data */ + if (host->pdata->flags & TMIO_MMC_32BIT_DATA_PORT) { + u8 data[4] = { }; + + if (is_read) + sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, (u32 *)buf, + count >> 2); + else + sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, (u32 *)buf, + count >> 2); + + /* if count was multiple of 4 */ + if (!(count & 0x3)) + return; + + buf8 = (u8 *)(buf + (count >> 2)); + count %= 4; + + if (is_read) { + sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, + (u32 *)data, 1); + memcpy(buf8, data, count); + } else { + memcpy(data, buf8, count); + sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, + (u32 *)data, 1); + } + + return; + } + if (is_read) sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1); else diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h index 3b95dc7..0dbcb7e 100644 --- a/include/linux/mfd/tmio.h +++ b/include/linux/mfd/tmio.h @@ -100,6 +100,11 @@ #define TMIO_MMC_SDIO_STATUS_QUIRK (1 << 8) /* + * Some controllers have a 32-bit wide data port register + */ +#define TMIO_MMC_32BIT_DATA_PORT (1 << 9) + +/* * Some controllers allows to set SDx actual clock */ #define TMIO_MMC_CLK_ACTUAL (1 << 10)