From patchwork Fri Jan 27 23:08:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 9542871 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CE27860415 for ; Fri, 27 Jan 2017 23:17:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B94E726E98 for ; Fri, 27 Jan 2017 23:17:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9A43127FBB; Fri, 27 Jan 2017 23:17:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9766726E98 for ; Fri, 27 Jan 2017 23:17:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750757AbdA0XRF (ORCPT ); Fri, 27 Jan 2017 18:17:05 -0500 Received: from mail-oi0-f67.google.com ([209.85.218.67]:35714 "EHLO mail-oi0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750724AbdA0XRE (ORCPT ); Fri, 27 Jan 2017 18:17:04 -0500 Received: by mail-oi0-f67.google.com with SMTP id x84so21692764oix.2; Fri, 27 Jan 2017 15:17:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=5KBJOACoBHS+F9+R+TrCNlwrEaAaRSZWjAGHXzvK1ZQ=; b=LndOKFpE9yQS6OEKZGSBsJVDL7sLEB6lqfPwVYhGfAPDYOs6E6IIuyO3yW26WKdfa0 J2pi6ttniA15/8Oxil+dICoqbPtnjG7/QUuorwzos2Jfn6Tig5N2CnW1jd4h95g3U51e EsyqPJ+OFwNDBl6O1w+zlQoz4sV1Xvip3mAsSr/qwG6+SR1MgtP9j9uNidosKBOKO/63 xE+yBku50R43rXQK6s1f7M2Rrqn0s/QVovPIhRp/8z+73Ak1qrlECz2l18HGTFws/Xsj Lugwh5ZtkRW7RHtenBXWcnu8sT+uLBBaI8NjJWC0UAV3TUea1eNEcq4v67lumVaq3VYj fRYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=5KBJOACoBHS+F9+R+TrCNlwrEaAaRSZWjAGHXzvK1ZQ=; b=glTWvsZqt0yrRran/rtC83S0txmeby6aCiM6HGnCAfbLhVzXQTK38msZPIafIIgFcs VJlMgdd/dRloQt2dc7vZrWQ8MUuS7fFc6hNY0XRnemw1g5ORQSorfrHgMth+Lo1lu48M t4gon85hvoZnwUlaqon7XKSd1GEaDAF67fP/bGU2qdYuxNaT784fe1tKht2d8tzaLxom 82eohhn89c7Mhp4pA7WO1LT37vvMfPx+21Cid/LTtKiDNwjZ5Q5d7lA6dbfdDTdykmWV 1XU45ig48+5kuC9fTEPd8bxB663VllDxvoXTbJ9Tvo7cu46/jKjNNMWQwpHajL3+l4yW E+pA== X-Gm-Message-State: AIkVDXIfjTeLIpbuPyjPoX4VSbAQN0+iGJs7xzUQYNrBQfSDzvP3Ia6AH0iukw2egm7XYA== X-Received: by 10.202.108.84 with SMTP id h81mr5630168oic.10.1485558539184; Fri, 27 Jan 2017 15:08:59 -0800 (PST) Received: from kurokawa.lan ([195.140.253.167]) by smtp.gmail.com with ESMTPSA id o6sm3098153oig.8.2017.01.27.15.08.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jan 2017 15:08:58 -0800 (PST) From: Marek Vasut To: linux-iio@vger.kernel.org Cc: Marek Vasut , Geert Uytterhoeven , Simon Horman , Jonathan Cameron , linux-renesas-soc@vger.kernel.org, Wolfram Sang , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH 1/2] iio: adc: Add Renesas GyroADC bindings Date: Sat, 28 Jan 2017 00:08:36 +0100 Message-Id: <20170127230837.9322-1-marek.vasut@gmail.com> X-Mailer: git-send-email 2.11.0 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Marek Vasut Add DT bindings for the Renesas RCar GyroADC block. This block is a simple 4/8-channel ADC which samples 12/15/24 bits of data every cycle from all channels. Signed-off-by: Marek Vasut Cc: Geert Uytterhoeven Cc: Simon Horman Cc: Jonathan Cameron Cc: linux-renesas-soc@vger.kernel.org Cc: Wolfram Sang Cc: Rob Herring Acked-by: Rob Herring Cc: devicetree@vger.kernel.org --- V8: - Sync the version with the 2/2 driver patch - Drop status prop from example - Add GyroADC block description - Enumerate the compatible string values - Make subnodes mandatory V9: - Replace &adc with adc@e6e54000 - Add Rob's ACK --- .../bindings/iio/adc/renesas,gyroadc.txt | 99 ++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt b/Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt new file mode 100644 index 000000000000..f5b0adae6010 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt @@ -0,0 +1,99 @@ +* Renesas RCar GyroADC device driver + +The GyroADC block is a reduced SPI block with up to 8 chipselect lines, +which supports the SPI protocol of a selected few SPI ADCs. The SPI ADCs +are sampled by the GyroADC block in a round-robin fashion and the result +presented in the GyroADC registers. + +Required properties: +- compatible: Should be "", "renesas,rcar-gyroadc". + The should be one of: + renesas,r8a7791-gyroadc - for the GyroADC block present + in r8a7791 SoC + renesas,r8a7792-gyroadc - for the GyroADC with interrupt + block present in r8a7792 SoC +- reg: Address and length of the register set for the device +- clocks: References to all the clocks specified in the clock-names + property as specified in + Documentation/devicetree/bindings/clock/clock-bindings.txt. +- clock-names: Shall contain "fck" and "if". The "fck" is the GyroADC block + clock, the "if" is the interface clock. +- power-domains: Must contain a reference to the PM domain, if available. +- #address-cells: Should be <1> (setting for the subnodes) for all ADCs + except for "fujitsu,mb88101a". Should be <0> (setting for + only subnode) for "fujitsu,mb88101a". +- #size-cells: Should be <0> (setting for the subnodes) + +Sub-nodes: +You must define subnode(s) which select the connected ADC type and reference +voltage for the GyroADC channels. + +Required properties for subnodes: +- compatible: Should be either of: + "fujitsu,mb88101a" + - Fujitsu MB88101A compatible mode, + 12bit sampling, up to 4 channels can be sampled in + round-robin fashion. One Fujitsu chip supplies four + GyroADC channels with data as it contains four ADCs + on the chip and thus for 4-channel operation, single + MB88101A is required. The Cx chipselect lines of the + MB88101A connect directly to two CHS lines of the + GyroADC, no demuxer is required. The data out line + of each MB88101A connects to a shared input pin of + the GyroADC. + "ti,adcs7476" or "ti,adc121" or "adi,ad7476" + - TI ADCS7476 / TI ADC121 / ADI AD7476 compatible mode, + 15bit sampling, up to 8 channels can be sampled in + round-robin fashion. One TI/ADI chip supplies single + ADC channel with data, thus for 8-channel operation, + 8 chips are required. A 3:8 chipselect demuxer is + required to connect the nCS line of the TI/ADI chips + to the GyroADC, while MISO line of each TI/ADI ADC + connects to a shared input pin of the GyroADC. + "maxim,max1162" or "maxim,max11100" + - Maxim MAX1162 / Maxim MAX11100 compatible mode, + 16bit sampling, up to 8 channels can be sampled in + round-robin fashion. One Maxim chip supplies single + ADC channel with data, thus for 8-channel operation, + 8 chips are required. A 3:8 chipselect demuxer is + required to connect the nCS line of the MAX chips + to the GyroADC, while MISO line of each Maxim ADC + connects to a shared input pin of the GyroADC. +- reg: Should be the number of the analog input. Should be present + for all ADCs except "fujitsu,mb88101a". +- vref-supply: Reference to the channel reference voltage regulator. + +Example: + vref_max1162: regulator-vref-max1162 { + compatible = "regulator-fixed"; + + regulator-name = "MAX1162 Vref"; + regulator-min-microvolt = <4096000>; + regulator-max-microvolt = <4096000>; + }; + + adc@e6e54000 { + compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc"; + reg = <0 0xe6e54000 0 64>; + clocks = <&mstp9_clks R8A7791_CLK_GYROADC>, <&clk_65m>; + clock-names = "fck", "if"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + + pinctrl-0 = <&adc_pins>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + reg = <0>; + compatible = "maxim,max1162"; + vref-supply = <&vref_max1162>; + }; + + adc@1 { + reg = <1>; + compatible = "maxim,max1162"; + vref-supply = <&vref_max1162>; + }; + };