From patchwork Thu Feb 2 21:20:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 9553245 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 556BC604E1 for ; Thu, 2 Feb 2017 21:21:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3FE8524603 for ; Thu, 2 Feb 2017 21:21:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 348ED266F3; Thu, 2 Feb 2017 21:21:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 94D4624603 for ; Thu, 2 Feb 2017 21:21:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751467AbdBBVVh (ORCPT ); Thu, 2 Feb 2017 16:21:37 -0500 Received: from relmlor1.renesas.com ([210.160.252.171]:12419 "EHLO relmlie4.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751458AbdBBVVg (ORCPT ); Thu, 2 Feb 2017 16:21:36 -0500 Received: from unknown (HELO relmlir3.idc.renesas.com) ([10.200.68.153]) by relmlie4.idc.renesas.com with ESMTP; 03 Feb 2017 06:21:34 +0900 Received: from relmlac4.idc.renesas.com (relmlac4.idc.renesas.com [10.200.69.24]) by relmlir3.idc.renesas.com (Postfix) with ESMTP id AE7C15DDBA; Fri, 3 Feb 2017 06:21:34 +0900 (JST) Received: by relmlac4.idc.renesas.com (Postfix, from userid 0) id 978A648014; Fri, 3 Feb 2017 06:21:34 +0900 (JST) Received: from relmlac4.idc.renesas.com (localhost [127.0.0.1]) by relmlac4.idc.renesas.com (Postfix) with ESMTP id 9709A480A6; Fri, 3 Feb 2017 06:21:34 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac4.idc.renesas.com with ESMTP id GAB06866; Fri, 3 Feb 2017 06:21:34 +0900 X-IronPort-AV: E=Sophos;i="5.33,326,1477926000"; d="scan'208";a="233346905" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii2.idc.renesas.com with ESMTP; 03 Feb 2017 06:21:33 +0900 Received: from localhost.localdomain (unknown [143.103.58.83]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id C38B3297; Thu, 2 Feb 2017 21:21:27 +0000 (UTC) From: Chris Brandt To: Simon Horman , Magnus Damm , Geert Uytterhoeven , Rob Herring , Mark Rutland , Russell King Cc: devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Brandt Subject: [PATCH] ARM: shmobile: r7s72100: Enable L2 cache Date: Thu, 2 Feb 2017 16:20:00 -0500 Message-Id: <20170202212000.10768-1-chris.brandt@renesas.com> X-Mailer: git-send-email 2.10.1 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This enables the 128KB L2 cache in the RZ/A1 (R7S72100). The 'Write full line of zeros mode' of this Cortex-A9 cannot be used because the sideband signals between the CA9 and PL310 are not connected. Since there is no option to disable this feature in the cache-l2x0 driver, our only option is to specify a secure write function which will then cause the cache-l2x0 driver to not enable this feature. If you do not override a l2c_write_sec function which causes the line of zeros mode to be enabled, then the system will crash pretty quickly after the L2C is enabled. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r7s72100.dtsi | 9 +++++++++ arch/arm/mach-shmobile/setup-r7s72100.c | 21 +++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 74e684f..08aaaff 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -177,6 +177,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <400000000>; + next-level-cache = <&L2>; }; }; @@ -368,6 +369,14 @@ <0xe8202000 0x1000>; }; + L2: cache-controller@3ffff000 { + compatible = "arm,pl310-cache"; + reg = <0x3ffff000 0x1000>; + interrupts = ; + cache-unified; + cache-level = <2>; + }; + i2c0: i2c@fcfee000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c index d46639f..655deba 100644 --- a/arch/arm/mach-shmobile/setup-r7s72100.c +++ b/arch/arm/mach-shmobile/setup-r7s72100.c @@ -15,6 +15,7 @@ */ #include +#include #include @@ -25,7 +26,27 @@ static const char *const r7s72100_boards_compat_dt[] __initconst = { NULL, }; +/* + * The 'Write full line of zeros mode' of this Cortex-A9 cannot be used because + * the sideband signals between the CA9 and PL310 are not connected. Since there + * is no option to disable this feature in the cache-l2x0 driver, our only + * option is to specify a secure write function which will then cause the + * cache-l2x0 driver to not enable this feature. + */ +static void r7s72100_l2c_write_sec(unsigned long val, unsigned int reg) +{ + static void __iomem *base; + + if (!base) + base = ioremap_nocache(0x3ffff000, SZ_4K); + + writel_relaxed(val, base + reg); +} + DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)") + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, + .l2c_write_sec = r7s72100_l2c_write_sec, .init_early = shmobile_init_delay, .init_late = shmobile_init_late, .dt_compat = r7s72100_boards_compat_dt,