From patchwork Tue Feb 7 17:09:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 9560701 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1D740602B1 for ; Tue, 7 Feb 2017 17:10:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0DA1C1FE95 for ; Tue, 7 Feb 2017 17:10:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0011B28434; Tue, 7 Feb 2017 17:10:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7F46E1FE95 for ; Tue, 7 Feb 2017 17:10:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754173AbdBGRKB (ORCPT ); Tue, 7 Feb 2017 12:10:01 -0500 Received: from relmlor1.renesas.com ([210.160.252.171]:61917 "EHLO relmlie4.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753497AbdBGRKA (ORCPT ); Tue, 7 Feb 2017 12:10:00 -0500 Received: from unknown (HELO relmlir1.idc.renesas.com) ([10.200.68.151]) by relmlie4.idc.renesas.com with ESMTP; 08 Feb 2017 02:09:58 +0900 Received: from relmlac4.idc.renesas.com (relmlac4.idc.renesas.com [10.200.69.24]) by relmlir1.idc.renesas.com (Postfix) with ESMTP id 29F7F4B5B2; Wed, 8 Feb 2017 02:09:58 +0900 (JST) Received: by relmlac4.idc.renesas.com (Postfix, from userid 0) id 287D4480A6; Wed, 8 Feb 2017 02:09:58 +0900 (JST) Received: from relmlac4.idc.renesas.com (localhost [127.0.0.1]) by relmlac4.idc.renesas.com (Postfix) with ESMTP id 15C60480A9; Wed, 8 Feb 2017 02:09:58 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac4.idc.renesas.com with ESMTP id CAB24204; Wed, 8 Feb 2017 02:09:58 +0900 X-IronPort-AV: E=Sophos;i="5.33,346,1477926000"; d="scan'208";a="233051789" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii1.idc.renesas.com with ESMTP; 08 Feb 2017 02:09:55 +0900 Received: from localhost.localdomain (unknown [172.27.49.108]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id D6C663CC; Tue, 7 Feb 2017 17:09:49 +0000 (UTC) From: Chris Brandt To: Simon Horman , Magnus Damm , Geert Uytterhoeven , Rob Herring , Mark Rutland , Russell King , Brad Mouring , Andrey Smirnov , Arnd Bergmann , Richard Cochran Cc: devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Brandt Subject: [PATCH v2 1/3] ARM: l2c: add pl310-no-sideband option Date: Tue, 7 Feb 2017 12:09:27 -0500 Message-Id: <20170207170929.29525-2-chris.brandt@renesas.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170207170929.29525-1-chris.brandt@renesas.com> References: <20170207170929.29525-1-chris.brandt@renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If a PL310 is added to a system, but the sideband signals are not connected, some Cortex A9 optimizations cannot be used. In particular, enabling Full Line Zeros in the CA9 without sidebands connected will crash the system since the CA9 will expect the L2C to perform operations, yet the L2C never gets the commands. Signed-off-by: Chris Brandt --- Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++ arch/arm/mm/cache-l2x0.c | 9 +++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt index 917199f..85046d2 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt @@ -90,6 +90,8 @@ Optional properties: - arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable), <1> (forcibly enable), property absent (OS specific behavior, preferably retain firmware settings) +- arm,pl310-no-sideband : disable all features that require sideband signals to + be connected between the CPU and L2 (PL310 only). Example: diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 2290be3..c744ac4 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -57,6 +57,8 @@ static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; struct l2x0_regs l2x0_saved_regs; +static bool l2x0_no_sideband; + /* * Common code for all cache controllers. */ @@ -620,7 +622,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock) u32 aux = l2x0_saved_regs.aux_ctrl; if (rev >= L310_CACHE_ID_RTL_R2P0) { - if (cortex_a9) { + if (cortex_a9 && !l2x0_no_sideband) { aux |= L310_AUX_CTRL_EARLY_BRESP; pr_info("L2C-310 enabling early BRESP for Cortex-A9\n"); } else if (aux & L310_AUX_CTRL_EARLY_BRESP) { @@ -629,7 +631,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock) } } - if (cortex_a9) { + if (cortex_a9 && !l2x0_no_sideband) { u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL); u32 acr = get_auxcr(); @@ -1200,6 +1202,9 @@ static void __init l2c310_of_parse(const struct device_node *np, *aux_mask &= ~L2C_AUX_CTRL_PARITY_ENABLE; } + if (of_property_read_bool(np, "arm,pl310-no-sideband")) + l2x0_no_sideband = true; + prefetch = l2x0_saved_regs.prefetch_ctrl; ret = of_property_read_u32(np, "arm,double-linefill", &val);