From patchwork Tue Feb 7 17:09:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 9560703 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 986FE602B1 for ; Tue, 7 Feb 2017 17:10:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8AA7428434 for ; Tue, 7 Feb 2017 17:10:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7EEEF28438; Tue, 7 Feb 2017 17:10:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6DD5A205FD for ; Tue, 7 Feb 2017 17:10:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754199AbdBGRKD (ORCPT ); Tue, 7 Feb 2017 12:10:03 -0500 Received: from relmlor4.renesas.com ([210.160.252.174]:41932 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753840AbdBGRKB (ORCPT ); Tue, 7 Feb 2017 12:10:01 -0500 Received: from unknown (HELO relmlir4.idc.renesas.com) ([10.200.68.154]) by relmlie3.idc.renesas.com with ESMTP; 08 Feb 2017 02:10:00 +0900 Received: from relmlac3.idc.renesas.com (relmlac3.idc.renesas.com [10.200.69.23]) by relmlir4.idc.renesas.com (Postfix) with ESMTP id 318CE3D645; Wed, 8 Feb 2017 02:10:00 +0900 (JST) Received: by relmlac3.idc.renesas.com (Postfix, from userid 0) id 3154E18070; Wed, 8 Feb 2017 02:10:00 +0900 (JST) Received: from relmlac3.idc.renesas.com (localhost [127.0.0.1]) by relmlac3.idc.renesas.com (Postfix) with ESMTP id 2AB901806F; Wed, 8 Feb 2017 02:10:00 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac3.idc.renesas.com with ESMTP id CAE09507; Wed, 8 Feb 2017 02:10:00 +0900 X-IronPort-AV: E=Sophos;i="5.33,346,1477926000"; d="scan'208";a="233051798" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii1.idc.renesas.com with ESMTP; 08 Feb 2017 02:09:58 +0900 Received: from localhost.localdomain (unknown [172.27.49.108]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id 72BB7372; Tue, 7 Feb 2017 17:09:52 +0000 (UTC) From: Chris Brandt To: Simon Horman , Magnus Damm , Geert Uytterhoeven , Rob Herring , Mark Rutland , Russell King , Brad Mouring , Andrey Smirnov , Arnd Bergmann , Richard Cochran Cc: devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Brandt Subject: [PATCH v2 3/3] ARM: dts: r7s72100: add l2 cache Date: Tue, 7 Feb 2017 12:09:29 -0500 Message-Id: <20170207170929.29525-4-chris.brandt@renesas.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170207170929.29525-1-chris.brandt@renesas.com> References: <20170207170929.29525-1-chris.brandt@renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Note that arm,pl301-no-sideband is required because the sideband signals between the CPU and L2C were not connected in this SoC. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- v2: * added "arm,pl310-no-sideband" --- arch/arm/boot/dts/r7s72100.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 74e684f..00b9972 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -177,6 +177,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <400000000>; + next-level-cache = <&L2>; }; }; @@ -368,6 +369,15 @@ <0xe8202000 0x1000>; }; + L2: cache-controller@3ffff000 { + compatible = "arm,pl310-cache"; + reg = <0x3ffff000 0x1000>; + interrupts = ; + arm,pl310-no-sideband; + cache-unified; + cache-level = <2>; + }; + i2c0: i2c@fcfee000 { #address-cells = <1>; #size-cells = <0>;