From patchwork Thu Feb 16 15:37:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 9577469 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0B7D16049F for ; Thu, 16 Feb 2017 15:38:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F1B06285BC for ; Thu, 16 Feb 2017 15:38:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E643928616; Thu, 16 Feb 2017 15:38:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 46C1D285BC for ; Thu, 16 Feb 2017 15:38:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932247AbdBPPiE (ORCPT ); Thu, 16 Feb 2017 10:38:04 -0500 Received: from relmlor4.renesas.com ([210.160.252.174]:60787 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932123AbdBPPiD (ORCPT ); Thu, 16 Feb 2017 10:38:03 -0500 Received: from unknown (HELO relmlir4.idc.renesas.com) ([10.200.68.154]) by relmlie3.idc.renesas.com with ESMTP; 17 Feb 2017 00:38:02 +0900 Received: from relmlac3.idc.renesas.com (relmlac3.idc.renesas.com [10.200.69.23]) by relmlir4.idc.renesas.com (Postfix) with ESMTP id 124316DC38; Fri, 17 Feb 2017 00:38:02 +0900 (JST) Received: by relmlac3.idc.renesas.com (Postfix, from userid 0) id 00EE018070; Fri, 17 Feb 2017 00:38:01 +0900 (JST) Received: from relmlac3.idc.renesas.com (localhost [127.0.0.1]) by relmlac3.idc.renesas.com (Postfix) with ESMTP id EEB081806F; Fri, 17 Feb 2017 00:38:01 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac3.idc.renesas.com with ESMTP id AAA10222; Fri, 17 Feb 2017 00:38:01 +0900 X-IronPort-AV: E=Sophos;i="5.35,169,1483974000"; d="scan'208";a="234784432" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii2.idc.renesas.com with ESMTP; 17 Feb 2017 00:38:00 +0900 Received: from localhost.localdomain (unknown [143.103.58.208]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id AD6773CC; Thu, 16 Feb 2017 15:37:53 +0000 (UTC) From: Chris Brandt To: Simon Horman , Magnus Damm , Geert Uytterhoeven , Rob Herring , Mark Rutland , Russell King , Brad Mouring , Andrey Smirnov , Arnd Bergmann , Richard Cochran Cc: devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Brandt Subject: [PATCH v3 1/3] ARM: l2c: allow CA9 optimizations to be disabled Date: Thu, 16 Feb 2017 10:37:24 -0500 Message-Id: <20170216153726.22919-2-chris.brandt@renesas.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170216153726.22919-1-chris.brandt@renesas.com> References: <20170216153726.22919-1-chris.brandt@renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If a PL310 is added to a system, but the sideband signals are not connected, some Cortex A9 optimizations cannot be used. In particular, enabling Full Line of Zeros in the CA9 without sidebands connected will crash the system since the CA9 will expect the L2C to perform operations, yet the L2C never gets the commands. Early BRESP also does not work without sideband signals. Signed-off-by: Chris Brandt --- v2: * split "arm,pl310-no-sideband" into "arm,early-bresp-disable" and "arm,full-line-zero-disable" --- Documentation/devicetree/bindings/arm/l2c2x0.txt | 3 +++ arch/arm/mm/cache-l2x0.c | 13 +++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt index 917199f..d9650c1 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt @@ -90,6 +90,9 @@ Optional properties: - arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable), <1> (forcibly enable), property absent (OS specific behavior, preferably retain firmware settings) +- arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310) +- arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero + write (PL310) Example: diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 2290be3..486cc6d 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -57,6 +57,9 @@ static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; struct l2x0_regs l2x0_saved_regs; +static bool l2x0_bresp_dis; +static bool l2x0_flz_dis; + /* * Common code for all cache controllers. */ @@ -620,7 +623,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock) u32 aux = l2x0_saved_regs.aux_ctrl; if (rev >= L310_CACHE_ID_RTL_R2P0) { - if (cortex_a9) { + if (cortex_a9 && !l2x0_bresp_dis) { aux |= L310_AUX_CTRL_EARLY_BRESP; pr_info("L2C-310 enabling early BRESP for Cortex-A9\n"); } else if (aux & L310_AUX_CTRL_EARLY_BRESP) { @@ -629,7 +632,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock) } } - if (cortex_a9) { + if (cortex_a9 && !l2x0_flz_dis) { u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL); u32 acr = get_auxcr(); @@ -1200,6 +1203,12 @@ static void __init l2c310_of_parse(const struct device_node *np, *aux_mask &= ~L2C_AUX_CTRL_PARITY_ENABLE; } + if (of_property_read_bool(np, "arm,early-bresp-disable")) + l2x0_bresp_dis = true; + + if (of_property_read_bool(np, "arm,full-line-zero-disable")) + l2x0_flz_dis = true; + prefetch = l2x0_saved_regs.prefetch_ctrl; ret = of_property_read_u32(np, "arm,double-linefill", &val);