From patchwork Thu Feb 16 16:17:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 9577689 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 41AE660589 for ; Thu, 16 Feb 2017 16:19:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 35A6F2862E for ; Thu, 16 Feb 2017 16:19:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2A22B28636; Thu, 16 Feb 2017 16:19:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6A72F28630 for ; Thu, 16 Feb 2017 16:19:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932465AbdBPQTG (ORCPT ); Thu, 16 Feb 2017 11:19:06 -0500 Received: from relmlor4.renesas.com ([210.160.252.174]:9176 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932386AbdBPQTE (ORCPT ); Thu, 16 Feb 2017 11:19:04 -0500 Received: from unknown (HELO relmlir1.idc.renesas.com) ([10.200.68.151]) by relmlie3.idc.renesas.com with ESMTP; 17 Feb 2017 01:19:03 +0900 Received: from relmlac2.idc.renesas.com (relmlac2.idc.renesas.com [10.200.69.22]) by relmlir1.idc.renesas.com (Postfix) with ESMTP id E95CA463CC; Fri, 17 Feb 2017 01:19:03 +0900 (JST) Received: by relmlac2.idc.renesas.com (Postfix, from userid 0) id E3E2F28076; Fri, 17 Feb 2017 01:19:03 +0900 (JST) Received: from relmlac2.idc.renesas.com (localhost [127.0.0.1]) by relmlac2.idc.renesas.com (Postfix) with ESMTP id DDAF028070; Fri, 17 Feb 2017 01:19:03 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac2.idc.renesas.com with ESMTP id BAA26851; Fri, 17 Feb 2017 01:19:03 +0900 X-IronPort-AV: E=Sophos;i="5.35,169,1483974000"; d="scan'208";a="234013172" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii1.idc.renesas.com with ESMTP; 17 Feb 2017 01:19:01 +0900 Received: from localhost.localdomain (unknown [143.103.58.208]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id 14A243CC; Thu, 16 Feb 2017 16:18:54 +0000 (UTC) From: Chris Brandt To: Simon Horman , Magnus Damm , Geert Uytterhoeven , Rob Herring , Mark Rutland , Russell King , Brad Mouring , Andrey Smirnov , Arnd Bergmann , Richard Cochran Cc: devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Brandt Subject: [PATCH v4 3/3] ARM: dts: r7s72100: add l2 cache Date: Thu, 16 Feb 2017 11:17:42 -0500 Message-Id: <20170216161742.29320-4-chris.brandt@renesas.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170216161742.29320-1-chris.brandt@renesas.com> References: <20170216161742.29320-1-chris.brandt@renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Note that early-bresp-disable and full-line-zero-disable are required because the sideband signals between the CPU and L2C were not connected in this SoC. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- v3: * split "arm,pl310-no-sideband" into "arm,early-bresp-disable" and "arm,full-line-zero-disable" v2: * added "arm,pl310-no-sideband" --- arch/arm/boot/dts/r7s72100.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 614ba79..ed62e19 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -180,6 +180,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <400000000>; + next-level-cache = <&L2>; }; }; @@ -371,6 +372,16 @@ <0xe8202000 0x1000>; }; + L2: cache-controller@3ffff000 { + compatible = "arm,pl310-cache"; + reg = <0x3ffff000 0x1000>; + interrupts = ; + arm,early-bresp-disable; + arm,full-line-zero-disable; + cache-unified; + cache-level = <2>; + }; + i2c0: i2c@fcfee000 { #address-cells = <1>; #size-cells = <0>;