From patchwork Wed Mar 29 17:30:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 9652025 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 17185602C8 for ; Wed, 29 Mar 2017 17:31:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0F596284DD for ; Wed, 29 Mar 2017 17:31:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 042E3284F6; Wed, 29 Mar 2017 17:31:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AA8AB284DD for ; Wed, 29 Mar 2017 17:31:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752868AbdC2RbQ (ORCPT ); Wed, 29 Mar 2017 13:31:16 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:47620 "EHLO relmlie4.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932098AbdC2RbO (ORCPT ); Wed, 29 Mar 2017 13:31:14 -0400 Received: from unknown (HELO relmlir1.idc.renesas.com) ([10.200.68.151]) by relmlie4.idc.renesas.com with ESMTP; 30 Mar 2017 02:31:12 +0900 Received: from relmlac2.idc.renesas.com (relmlac2.idc.renesas.com [10.200.69.22]) by relmlir1.idc.renesas.com (Postfix) with ESMTP id C94D348D14; Thu, 30 Mar 2017 02:31:12 +0900 (JST) Received: by relmlac2.idc.renesas.com (Postfix, from userid 0) id BCF3528076; Thu, 30 Mar 2017 02:31:12 +0900 (JST) Received: from relmlac2.idc.renesas.com (localhost [127.0.0.1]) by relmlac2.idc.renesas.com (Postfix) with ESMTP id B46F828070; Thu, 30 Mar 2017 02:31:12 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac2.idc.renesas.com with ESMTP id CAC28101; Thu, 30 Mar 2017 02:31:12 +0900 X-IronPort-AV: E=Sophos;i="5.36,242,1486393200"; d="scan'208";a="238139442" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii1.idc.renesas.com with ESMTP; 30 Mar 2017 02:31:11 +0900 Received: from localhost.localdomain (unknown [172.27.49.222]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id 6A2EEA1; Wed, 29 Mar 2017 17:31:10 +0000 (UTC) From: Chris Brandt To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Mark Rutland , Simon Horman , Geert Uytterhoeven Cc: rtc-linux@googlegroups.com, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Brandt Subject: [PATCH v3 4/7] ARM: dts: r7s72100: add RTC_X clock inputs to device tree Date: Wed, 29 Mar 2017 10:30:32 -0700 Message-Id: <20170329173035.67477-5-chris.brandt@renesas.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170329173035.67477-1-chris.brandt@renesas.com> References: <20170329173035.67477-1-chris.brandt@renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the RTC clocks to device tree. The frequencies must be fixed values according to the hardware manual. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r7s72100.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 6a1448be4e10..632a6a481be8 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -51,6 +51,20 @@ clock-frequency = <0>; }; + rtc_x1_clk: rtc_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board to 32678 */ + clock-frequency = <0>; + }; + + rtc_x3_clk: rtc_x3 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board to 4000000 */ + clock-frequency = <0>; + }; + /* Fixed factor clocks */ b_clk: b { #clock-cells = <0>;