From patchwork Fri Jun 2 16:06:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 9762933 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C929360360 for ; Fri, 2 Jun 2017 16:07:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BC6DB28531 for ; Fri, 2 Jun 2017 16:07:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B116528557; Fri, 2 Jun 2017 16:07:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2293528531 for ; Fri, 2 Jun 2017 16:07:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751202AbdFBQH6 (ORCPT ); Fri, 2 Jun 2017 12:07:58 -0400 Received: from relmlor4.renesas.com ([210.160.252.174]:65304 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750955AbdFBQH6 (ORCPT ); Fri, 2 Jun 2017 12:07:58 -0400 Received: from unknown (HELO relmlir4.idc.renesas.com) ([10.200.68.154]) by relmlie3.idc.renesas.com with ESMTP; 03 Jun 2017 01:07:56 +0900 Received: from relmlii1.idc.renesas.com (relmlii1.idc.renesas.com [10.200.68.65]) by relmlir4.idc.renesas.com (Postfix) with ESMTP id 60846389E5; Sat, 3 Jun 2017 01:07:56 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.39,285,1493650800"; d="scan'208";a="245218411" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii1.idc.renesas.com with ESMTP; 03 Jun 2017 01:07:55 +0900 Received: from localhost.localdomain (unknown [143.103.58.195]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id A4A64EA; Fri, 2 Jun 2017 16:07:54 +0000 (UTC) From: Chris Brandt To: Simon Horman , Geert Uytterhoeven , Rob Herring , Mark Rutland Cc: devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Brandt Subject: [PATCH v2] ARM: dts: r7s72100: add clock bit definitions Date: Fri, 2 Jun 2017 09:06:49 -0700 Message-Id: <20170602160649.3120-1-chris.brandt@renesas.com> X-Mailer: git-send-email 2.13.0 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the remaining bit locations for the module stop clock registers. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- v2: * Added coresight bit * MCPWM -> PWM * SNDGEN[0-3] -> SG[0-3] * ETHABV -> ETHAVB * SPIMBC[0-1] -> SPIBSC[0-1] * Added SSI[0-5] --- include/dt-bindings/clock/r7s72100-clock.h | 51 ++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h index dcd2072151fc..7dd8bc0c3cd0 100644 --- a/include/dt-bindings/clock/r7s72100-clock.h +++ b/include/dt-bindings/clock/r7s72100-clock.h @@ -12,8 +12,18 @@ #define R7S72100_CLK_PLL 0 +/* MSTP2 */ +#define R7S72100_CLK_CORESIGHT 0 + /* MSTP3 */ +#define R7S72100_CLK_IEBUS 7 +#define R7S72100_CLK_IRDA 6 +#define R7S72100_CLK_LIN0 5 +#define R7S72100_CLK_LIN1 4 #define R7S72100_CLK_MTU2 3 +#define R7S72100_CLK_CAN 2 +#define R7S72100_CLK_ADCPWR 1 +#define R7S72100_CLK_PWM 0 /* MSTP4 */ #define R7S72100_CLK_SCIF0 7 @@ -26,25 +36,51 @@ #define R7S72100_CLK_SCIF7 0 /* MSTP5 */ +#define R7S72100_CLK_SCI0 7 +#define R7S72100_CLK_SCI1 6 +#define R7S72100_CLK_SG0 5 +#define R7S72100_CLK_SG1 4 +#define R7S72100_CLK_SG2 3 +#define R7S72100_CLK_SG3 2 #define R7S72100_CLK_OSTM0 1 #define R7S72100_CLK_OSTM1 0 /* MSTP6 */ +#define R7S72100_CLK_ADC 7 +#define R7S72100_CLK_CEU 6 +#define R7S72100_CLK_DOC0 5 +#define R7S72100_CLK_DOC1 4 +#define R7S72100_CLK_DRC0 3 +#define R7S72100_CLK_DRC1 2 +#define R7S72100_CLK_JCU 1 #define R7S72100_CLK_RTC 0 /* MSTP7 */ +#define R7S72100_CLK_VDEC0 7 +#define R7S72100_CLK_VDEC1 6 #define R7S72100_CLK_ETHER 4 +#define R7S72100_CLK_NAND 3 #define R7S72100_CLK_USB0 1 #define R7S72100_CLK_USB1 0 /* MSTP8 */ +#define R7S72100_CLK_IMR0 7 +#define R7S72100_CLK_IMR1 6 +#define R7S72100_CLK_IMRDISP 5 #define R7S72100_CLK_MMCIF 4 +#define R7S72100_CLK_MLB 3 +#define R7S72100_CLK_ETHAVB 2 +#define R7S72100_CLK_SCUX 1 /* MSTP9 */ #define R7S72100_CLK_I2C0 7 #define R7S72100_CLK_I2C1 6 #define R7S72100_CLK_I2C2 5 #define R7S72100_CLK_I2C3 4 +#define R7S72100_CLK_SPIBSC0 3 +#define R7S72100_CLK_SPIBSC1 2 +#define R7S72100_CLK_VDC50 1 /* and LVDS */ +#define R7S72100_CLK_VDC51 0 /* MSTP10 */ #define R7S72100_CLK_SPI0 7 @@ -52,6 +88,17 @@ #define R7S72100_CLK_SPI2 5 #define R7S72100_CLK_SPI3 4 #define R7S72100_CLK_SPI4 3 +#define R7S72100_CLK_CDROM 2 +#define R7S72100_CLK_SPDIF 1 +#define R7S72100_CLK_RGPVG2 0 + +/* MSTP11 */ +#define R7S72100_CLK_SSI0 5 +#define R7S72100_CLK_SSI1 4 +#define R7S72100_CLK_SSI2 3 +#define R7S72100_CLK_SSI3 2 +#define R7S72100_CLK_SSI4 1 +#define R7S72100_CLK_SSI5 0 /* MSTP12 */ #define R7S72100_CLK_SDHI00 3 @@ -59,4 +106,8 @@ #define R7S72100_CLK_SDHI10 1 #define R7S72100_CLK_SDHI11 0 +/* MSTP13 */ +#define R7S72100_CLK_PIX1 2 +#define R7S72100_CLK_PIX0 1 + #endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */