From patchwork Thu Jun 29 10:18:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 9816351 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 02238603F2 for ; Thu, 29 Jun 2017 10:19:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EB6C22869C for ; Thu, 29 Jun 2017 10:19:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E05D82869A; Thu, 29 Jun 2017 10:19:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7FCF5285D9 for ; Thu, 29 Jun 2017 10:19:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752584AbdF2KTm (ORCPT ); Thu, 29 Jun 2017 06:19:42 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:36334 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752563AbdF2KTl (ORCPT ); Thu, 29 Jun 2017 06:19:41 -0400 Received: by mail-wm0-f68.google.com with SMTP id y5so1632601wmh.3; Thu, 29 Jun 2017 03:19:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dagBcnuqrkc1bC+Vz3Gzexp364jwnz+kuRUP68n2o/M=; b=T9eQhfpbcrdWvcTo7ocUJJuSNfEX9B1ygmzS7n9PpiS4pcx6gTMcFVw3FrYbI4Ylw5 0RjgYxxxTLnP8vnzGLwIXqpOH7085DVwA3WnZF2KHHxoTyVhlaSM6ZOC5ScaPt1MxNBZ 3eZeX0M61JQlfakpxI2/VAarS1ef/wLk79NXm+oJRg0987qb/5BG/m2rNLk4vV51ujME 7Yl14tcyo+M8Pn1E7yQsktc5evCOJcAqVG2bZmKKTv4x/sFJx2mifMqlChy/DOAn6qlK mV5acQI5j97pwz1+G6b1NBKd75QiKnynypBiMVVAsSRxDqpjYx4+2LT3+wRd7jJbod1y EsEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dagBcnuqrkc1bC+Vz3Gzexp364jwnz+kuRUP68n2o/M=; b=AhXDvQwSDuHrM7QguqTPsFE62ml+IhSLeR5lI4iBF38043cFljINPH7pckpaDaxN1+ orK11a7DAE+07h34FZtFrSUz9MExi/5dwQmtFZyVitLaBoGdypNedKn3GvuFx78S4qcS ebkRLn2oEaKaFfLw28rrcN+xpJcIg0neAXqCuRbX4xxNaoLvgFphmyEExVPhkoM4a3UG GHGT27+a1MfKX0vvOn/VWVbRsGku9oYTk7nH78T07Odu+MpFudPypZF13e7W8f/0IrBM xxFTsh9xhHpgyRqi+qU5zvCI9lehBkviKftMJ7ksta6/hY8CHPqATfsEX5c7ssz1LXFT 4pJg== X-Gm-Message-State: AKS2vOyg+t/5lyfopfY3h5qGl/oTSEO6vTHSS/4syDV+PtyUX1ykz3qe HJeHtmOE+rHPJ0nmEr0= X-Received: by 10.28.137.146 with SMTP id l140mr10329001wmd.101.1498731579163; Thu, 29 Jun 2017 03:19:39 -0700 (PDT) Received: from chi.lan (cst-prg-169-255.cust.vodafone.cz. [46.135.169.255]) by smtp.gmail.com with ESMTPSA id t74sm7623653wmt.19.2017.06.29.03.19.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Jun 2017 03:19:38 -0700 (PDT) From: Marek Vasut To: linux-clk@vger.kernel.org Cc: Marek Vasut , Stephen Boyd , Alexey Firago , Michael Turquette , Laurent Pinchart , linux-renesas-soc@vger.kernel.org Subject: [PATCH 6/8] clk: vc5: Add support for the input frequency doubler Date: Thu, 29 Jun 2017 12:18:49 +0200 Message-Id: <20170629101851.23972-6-marek.vasut@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170629101851.23972-1-marek.vasut@gmail.com> References: <20170629101851.23972-1-marek.vasut@gmail.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Marek Vasut The VersaClock 6 has an input frequency doubler between the input clock mux and the predivider. Add new capability flag and support for this frequency doubler block into the driver. Signed-off-by: Marek Vasut Cc: Stephen Boyd Cc: Alexey Firago Cc: Michael Turquette Cc: Laurent Pinchart Cc: linux-renesas-soc@vger.kernel.org --- drivers/clk/clk-versaclock5.c | 78 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 77 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c index fcde42393997..6db84358520a 100644 --- a/drivers/clk/clk-versaclock5.c +++ b/drivers/clk/clk-versaclock5.c @@ -57,6 +57,7 @@ #define VC5_PRIM_SRC_SHDN 0x10 #define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7) #define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6) +#define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3) #define VC5_PRIM_SRC_SHDN_SP BIT(1) #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0) @@ -122,6 +123,8 @@ /* flags to describe chip features */ /* chip has built-in oscilator */ #define VC5_HAS_INTERNAL_XTAL BIT(0) +/* chip has PFD requency doubler */ +#define VC5_HAS_PFD_FREQ_DBL BIT(1) /* Supported IDT VC5 models. */ enum vc5_model { @@ -157,6 +160,7 @@ struct vc5_driver_data { struct clk *pin_clkin; unsigned char clk_mux_ins; struct clk_hw clk_mux; + struct clk_hw clk_mul; struct clk_hw clk_pfd; struct vc5_hw_data clk_pll; struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM]; @@ -167,6 +171,10 @@ static const char * const vc5_mux_names[] = { "mux" }; +static const char * const vc5_dbl_names[] = { + "dbl" +}; + static const char * const vc5_pfd_names[] = { "pfd" }; @@ -264,6 +272,54 @@ static const struct clk_ops vc5_mux_ops = { .get_parent = vc5_mux_get_parent, }; +static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct vc5_driver_data *vc5 = + container_of(hw, struct vc5_driver_data, clk_mul); + unsigned int premul; + + regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul); + if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ) + parent_rate *= 2; + + return parent_rate; +} + +static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + if ((*parent_rate == rate) || ((*parent_rate * 2) == rate)) + return rate; + else + return -EINVAL; +} + +static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct vc5_driver_data *vc5 = + container_of(hw, struct vc5_driver_data, clk_mul); + u32 mask; + + if ((parent_rate * 2) == rate) + mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ; + else + mask = 0; + + regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, + VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ, + mask); + + return 0; +} + +static const struct clk_ops vc5_dbl_ops = { + .recalc_rate = vc5_dbl_recalc_rate, + .round_rate = vc5_dbl_round_rate, + .set_rate = vc5_dbl_set_rate, +}; + static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -707,12 +763,32 @@ static int vc5_probe(struct i2c_client *client, goto err_clk; } + if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) { + /* Register frequency doubler */ + memset(&init, 0, sizeof(init)); + init.name = vc5_dbl_names[0]; + init.ops = &vc5_dbl_ops; + init.flags = CLK_SET_RATE_PARENT; + init.parent_names = vc5_mux_names; + init.num_parents = 1; + vc5->clk_mul.init = &init; + ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul); + if (ret) { + dev_err(&client->dev, "unable to register %s\n", + init.name); + goto err_clk; + } + } + /* Register PFD */ memset(&init, 0, sizeof(init)); init.name = vc5_pfd_names[0]; init.ops = &vc5_pfd_ops; init.flags = CLK_SET_RATE_PARENT; - init.parent_names = vc5_mux_names; + if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) + init.parent_names = vc5_dbl_names; + else + init.parent_names = vc5_mux_names; init.num_parents = 1; vc5->clk_pfd.init = &init; ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd);