diff mbox

[v3] i2c: riic: remove fixed clock restriction

Message ID 20171016183253.2291-1-chris.brandt@renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show

Commit Message

Chris Brandt Oct. 16, 2017, 6:32 p.m. UTC
Most systems with this i2c are going to have a clock of either 33.33MHz or
32MHz. That 4% difference is not reason enough to warrant that the driver
to completely fail.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
v3:
 * now check a range of safe frequencies
v2:
 * simplified error message.
---
---
 drivers/i2c/busses/i2c-riic.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

Comments

Chris Brandt Oct. 17, 2017, 8:31 p.m. UTC | #1
Hi Wolfram,

On Monday, October 16, 2017, Chris Brandt wrote:
> Most systems with this i2c are going to have a clock of either 33.33MHz or
> 32MHz. That 4% difference is not reason enough to warrant that the driver
> to completely fail.
> 
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> ---
> v3:
>  * now check a range of safe frequencies
> v2:
>  * simplified error message.
> ---

Actually, if you want to hold off on this patch, I'm almost done with a 
real fix which is to calculate any frequency based on current parent 
clock and rise/fall timings specified in the DT as you suggested.


Chris
Wolfram Sang Oct. 17, 2017, 10:03 p.m. UTC | #2
> Actually, if you want to hold off on this patch, I'm almost done with a 
> real fix which is to calculate any frequency based on current parent 
> clock and rise/fall timings specified in the DT as you suggested.

Sounds awesome! So, I'll wait a little how the formula goes. We can
always fall back to this patch if all fails... Thanks!
diff mbox

Patch

diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index c811af4c8d81..4c001d09aac2 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -299,12 +299,14 @@  static int riic_init_hw(struct riic_dev *riic, u32 spd)
 
 	/*
 	 * TODO: Implement formula to calculate the timing values depending on
-	 * variable parent clock rate and arbitrary bus speed
+	 * variable parent clock rate and arbitrary bus speed.
+	 * For now, just use calculations based on a 33.33MHz clock.
 	 */
 	rate = clk_get_rate(riic->clk);
-	if (rate != 33325000) {
+	if ((rate < 32000000) || (rate > 33400000)) {
 		dev_err(&riic->adapter.dev,
-			"invalid parent clk (%lu). Must be 33325000Hz\n", rate);
+			"invalid parent clk (%lu). Must be 32.0MHz-33.4MHz.\n",
+			rate);
 		clk_disable_unprepare(riic->clk);
 		return -EINVAL;
 	}