From patchwork Sun Apr 8 13:09:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 10328331 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3AD2D6020F for ; Sun, 8 Apr 2018 13:09:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2A9B328E5B for ; Sun, 8 Apr 2018 13:09:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1D68E28E65; Sun, 8 Apr 2018 13:09:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 898CF28E5B for ; Sun, 8 Apr 2018 13:09:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751549AbeDHNJr (ORCPT ); Sun, 8 Apr 2018 09:09:47 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:45301 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751423AbeDHNJq (ORCPT ); Sun, 8 Apr 2018 09:09:46 -0400 Received: by mail-wr0-f193.google.com with SMTP id u11so5709005wri.12; Sun, 08 Apr 2018 06:09:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=V/xPvHm8rurajbrR1lYDXmBBca3BQc1/IYjH81XoArM=; b=NY2y4hGaNZwejqrq44qd9MEbuHQQkSb/czF0kE+0PA2tggXI1LGjNbvr1+5ZdvzjPQ Hv6y1Lg3d6XTkb8l00T9SKsTj9EJg/CiH4sK3QLIBFal0avv/z6zaAb6ErkYOXk0hXPP ARGqN7etVHTdnHsa68dAwGnnQCYgrMrB647fgTyGC1Uak+OVIy6ZEJroanK+6xhoiGFN OKLHW0DUgCJsyAN4AcwKyqGiLry9YsGJLOHsMYq12PuSAwG9VKaPcLy5SncZSPX0PquI KSWuctODw6mdhc3D6acNDw1Tph5Puw7TXEM/PMRr5TWRW9NGta7ZCKPtDnlRLexMEwRY sGbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=V/xPvHm8rurajbrR1lYDXmBBca3BQc1/IYjH81XoArM=; b=hEDsAoIwwmK+Jq7A5C7SdwWhJWGITV+jYtd/bHMhojPflDC3O3dfNkhgtBGDWLaNkB pyF8zI72nmspgHVlaYDS+BNlSDjuVSSrWf+w0XlIR7nA4+JagzobuaeCsqE+ndXJPcjK dN/qcOiA6DIOXCe6wVaBLqSu19P+THWJdIWwFco1Q4u7eMdBySkhMPxKZBlRl/ocIQri tNTZoZyViv6phy1hNuWUSGfBK9NJDf1Na8q6lILxR1BeaUq4qeTBEKr9dPX4GetBGZYf uU9gcmjx95c4oSMzS3/4hrMaFRIj85Bt5UbEHDu5//wYSitYgqlmJscHruEvxvc77gTr vJCQ== X-Gm-Message-State: AElRT7Gg0VLnASoPXoIZ8nB97TXDZoxHmToFG4Fwu1k8qXE4eb4xxKOO Ye+xrrY5NZ2/r6Fj0EBDmx6ktaNd X-Google-Smtp-Source: AIpwx4+9fbDHjnIAA1uEDB7lp8ibeLIO5t+I53pMWVerJdKCMo3jrFMFir8eSSswzz3JP6TH5+vJDQ== X-Received: by 10.223.210.12 with SMTP id g12mr22690845wri.131.1523192984940; Sun, 08 Apr 2018 06:09:44 -0700 (PDT) Received: from kurokawa.lan (ip-86-49-107-50.net.upcbroadband.cz. [86.49.107.50]) by smtp.gmail.com with ESMTPSA id w62sm2337462wmb.6.2018.04.08.06.09.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 08 Apr 2018 06:09:44 -0700 (PDT) From: Marek Vasut X-Google-Original-From: Marek Vasut To: linux-pci@vger.kernel.org Cc: Marek Vasut , Geert Uytterhoeven , Phil Edworthy , Simon Horman , Wolfram Sang , linux-renesas-soc@vger.kernel.org Subject: [PATCH V2] PCI: rcar: Clean up the macros Date: Sun, 8 Apr 2018 15:09:42 +0200 Message-Id: <20180408130942.19148-1-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.16.2 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch replaces the (1 << n) with BIT(n) and cleans up whitespace, no functional change. Signed-off-by: Marek Vasut Cc: Geert Uytterhoeven Cc: Phil Edworthy Cc: Simon Horman Cc: Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org Reviewed-by: Niklas Söderlund --- V2: Reword the commit message --- drivers/pci/host/pcie-rcar.c | 52 ++++++++++++++++++++++---------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c index 25f68305322c..5ab7bf6a8de0 100644 --- a/drivers/pci/host/pcie-rcar.c +++ b/drivers/pci/host/pcie-rcar.c @@ -30,9 +30,9 @@ #define PCIECAR 0x000010 #define PCIECCTLR 0x000018 -#define CONFIG_SEND_ENABLE (1 << 31) +#define CONFIG_SEND_ENABLE BIT(31) #define TYPE0 (0 << 8) -#define TYPE1 (1 << 8) +#define TYPE1 BIT(8) #define PCIECDR 0x000020 #define PCIEMSR 0x000028 #define PCIEINTXR 0x000400 @@ -44,7 +44,7 @@ #define PCIETSTR 0x02004 #define DATA_LINK_ACTIVE 1 #define PCIEERRFR 0x02020 -#define UNSUPPORTED_REQUEST (1 << 4) +#define UNSUPPORTED_REQUEST BIT(4) #define PCIEMSIFR 0x02044 #define PCIEMSIALR 0x02048 #define MSIFE 1 @@ -57,17 +57,17 @@ /* local address reg & mask */ #define PCIELAR(x) (0x02200 + ((x) * 0x20)) #define PCIELAMR(x) (0x02208 + ((x) * 0x20)) -#define LAM_PREFETCH (1 << 3) -#define LAM_64BIT (1 << 2) -#define LAR_ENABLE (1 << 1) +#define LAM_PREFETCH BIT(3) +#define LAM_64BIT BIT(2) +#define LAR_ENABLE BIT(1) /* PCIe address reg & mask */ #define PCIEPALR(x) (0x03400 + ((x) * 0x20)) #define PCIEPAUR(x) (0x03404 + ((x) * 0x20)) #define PCIEPAMR(x) (0x03408 + ((x) * 0x20)) #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20)) -#define PAR_ENABLE (1 << 31) -#define IO_SPACE (1 << 8) +#define PAR_ENABLE BIT(31) +#define IO_SPACE BIT(8) /* Configuration */ #define PCICONF(x) (0x010000 + ((x) * 0x4)) @@ -79,23 +79,23 @@ #define IDSETR1 0x011004 #define TLCTLR 0x011048 #define MACSR 0x011054 -#define SPCHGFIN (1 << 4) -#define SPCHGFAIL (1 << 6) -#define SPCHGSUC (1 << 7) +#define SPCHGFIN BIT(4) +#define SPCHGFAIL BIT(6) +#define SPCHGSUC BIT(7) #define LINK_SPEED (0xf << 16) #define LINK_SPEED_2_5GTS (1 << 16) #define LINK_SPEED_5_0GTS (2 << 16) #define MACCTLR 0x011058 -#define SPEED_CHANGE (1 << 24) -#define SCRAMBLE_DISABLE (1 << 27) +#define SPEED_CHANGE BIT(24) +#define SCRAMBLE_DISABLE BIT(27) #define MACS2R 0x011078 #define MACCGSPSETR 0x011084 -#define SPCNGRSN (1 << 31) +#define SPCNGRSN BIT(31) /* R-Car H1 PHY */ #define H1_PCIEPHYADRR 0x04000c -#define WRITE_CMD (1 << 16) -#define PHY_ACK (1 << 24) +#define WRITE_CMD BIT(16) +#define PHY_ACK BIT(24) #define RATE_POS 12 #define LANE_POS 8 #define ADR_POS 0 @@ -107,19 +107,19 @@ #define GEN2_PCIEPHYDATA 0x784 #define GEN2_PCIEPHYCTRL 0x78c -#define INT_PCI_MSI_NR 32 +#define INT_PCI_MSI_NR 32 -#define RCONF(x) (PCICONF(0)+(x)) -#define RPMCAP(x) (PMCAP(0)+(x)) -#define REXPCAP(x) (EXPCAP(0)+(x)) -#define RVCCAP(x) (VCCAP(0)+(x)) +#define RCONF(x) (PCICONF(0) + (x)) +#define RPMCAP(x) (PMCAP(0) + (x)) +#define REXPCAP(x) (EXPCAP(0) + (x)) +#define RVCCAP(x) (VCCAP(0) + (x)) -#define PCIE_CONF_BUS(b) (((b) & 0xff) << 24) -#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19) -#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16) +#define PCIE_CONF_BUS(b) (((b) & 0xff) << 24) +#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19) +#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16) -#define RCAR_PCI_MAX_RESOURCES 4 -#define MAX_NR_INBOUND_MAPS 6 +#define RCAR_PCI_MAX_RESOURCES 4 +#define MAX_NR_INBOUND_MAPS 6 struct rcar_msi { DECLARE_BITMAP(used, INT_PCI_MSI_NR);