From patchwork Mon Sep 24 16:49:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 10612703 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 21A776CB for ; Mon, 24 Sep 2018 16:50:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 18C7D2A022 for ; Mon, 24 Sep 2018 16:50:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0D0492A02A; Mon, 24 Sep 2018 16:50:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9AE982A022 for ; Mon, 24 Sep 2018 16:50:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732367AbeIXWxU (ORCPT ); Mon, 24 Sep 2018 18:53:20 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:46921 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728006AbeIXWxU (ORCPT ); Mon, 24 Sep 2018 18:53:20 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie2.idc.renesas.com with ESMTP; 25 Sep 2018 01:50:14 +0900 Received: from relmlii2.idc.renesas.com (relmlii2.idc.renesas.com [10.200.68.66]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id 64306422DA; Tue, 25 Sep 2018 01:50:14 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.54,298,1534777200"; d="scan'208";a="293339470" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii2.idc.renesas.com with ESMTP; 25 Sep 2018 01:50:13 +0900 Received: from ubuntu.localdomain (unknown [143.103.58.87]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id 03B7C225; Mon, 24 Sep 2018 16:50:08 +0000 (UTC) From: Chris Brandt To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Simon Horman , Chris Brandt Subject: [PATCH v2 3/3] clk: renesas: r7s9210: Move table update to separate function Date: Mon, 24 Sep 2018 11:49:37 -0500 Message-Id: <20180924164937.36536-4-chris.brandt@renesas.com> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180924164937.36536-1-chris.brandt@renesas.com> References: <20180924164937.36536-1-chris.brandt@renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Same functionality, just easier to read. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r7s9210-cpg-mssr.c | 94 ++++++++++++++++++---------------- 1 file changed, 49 insertions(+), 45 deletions(-) diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c index 7ab9030ef8b9..f9c22b61883b 100644 --- a/drivers/clk/renesas/r7s9210-cpg-mssr.c +++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c @@ -97,6 +97,53 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = { }; +/* The clock dividers in the table vary based on DT and register settings */ +static void r7s9210_update_clk_table(struct clk *extal_clk, void __iomem *base) +{ + int i; + u16 frqcr; + u8 index; + + /* If EXTAL is above 12MHz, then we know it is Mode 1 */ + if (clk_get_rate(extal_clk) > 12000000) + cpg_mode = 1; + + frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF; + if (frqcr == 0x012) + index = 0; + else if (frqcr == 0x112) + index = 1; + else if (frqcr == 0x212) + index = 2; + else if (frqcr == 0x322) + index = 3; + else if (frqcr == 0x333) + index = 4; + else + BUG_ON(1); /* Illegal FRQCR value */ + + for (i = 0; i < ARRAY_SIZE(r7s9210_core_clks); i++) { + switch (r7s9210_core_clks[i].id) { + case R7S9210_CLK_I: + r7s9210_core_clks[i].div = ratio_tab[index].i; + break; + case R7S9210_CLK_G: + r7s9210_core_clks[i].div = ratio_tab[index].g; + break; + case R7S9210_CLK_B: + r7s9210_core_clks[i].div = ratio_tab[index].b; + break; + case R7S9210_CLK_P1: + case R7S9210_CLK_P1C: + r7s9210_core_clks[i].div = ratio_tab[index].p1; + break; + case R7S9210_CLK_P0: + r7s9210_core_clks[i].div = 32; + break; + } + } +} + struct clk * __init rza2_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core, const struct cpg_mssr_info *info, struct clk **clks, void __iomem *base, @@ -105,9 +152,6 @@ struct clk * __init rza2_cpg_clk_register(struct device *dev, struct clk *parent; unsigned int mult = 1; unsigned int div = 1; - u16 frqcr; - u8 index; - int i; parent = clks[core->parent]; if (IS_ERR(parent)) @@ -128,48 +172,8 @@ struct clk * __init rza2_cpg_clk_register(struct device *dev, return ERR_PTR(-EINVAL); } - /* Adjust the dividers based on the current FRQCR setting */ - if (core->id == CLK_MAIN) { - - /* If EXTAL is above 12MHz, then we know it is Mode 1 */ - if (clk_get_rate(parent) > 12000000) - cpg_mode = 1; - - frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF; - if (frqcr == 0x012) - index = 0; - else if (frqcr == 0x112) - index = 1; - else if (frqcr == 0x212) - index = 2; - else if (frqcr == 0x322) - index = 3; - else if (frqcr == 0x333) - index = 4; - else - BUG_ON(1); /* Illegal FRQCR value */ - - for (i = 0; i < ARRAY_SIZE(r7s9210_core_clks); i++) { - switch (r7s9210_core_clks[i].id) { - case R7S9210_CLK_I: - r7s9210_core_clks[i].div = ratio_tab[index].i; - break; - case R7S9210_CLK_G: - r7s9210_core_clks[i].div = ratio_tab[index].g; - break; - case R7S9210_CLK_B: - r7s9210_core_clks[i].div = ratio_tab[index].b; - break; - case R7S9210_CLK_P1: - case R7S9210_CLK_P1C: - r7s9210_core_clks[i].div = ratio_tab[index].p1; - break; - case R7S9210_CLK_P0: - r7s9210_core_clks[i].div = 32; - break; - } - } - } + if (core->id == CLK_MAIN) + r7s9210_update_clk_table(parent, base); return clk_register_fixed_factor(NULL, core->name, __clk_get_name(parent), 0, mult, div);