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[86.49.110.70]) by smtp.gmail.com with ESMTPSA id x142-v6sm85022167wmd.20.2018.11.20.15.32.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 15:32:54 -0800 (PST) From: Marek Vasut X-Google-Original-From: Marek Vasut To: devicetree@vger.kernel.org Cc: Takeshi Kihara , Marek Vasut , Geert Uytterhoeven , Marc Kleine-Budde , Rob Herring , Simon Horman , Wolfram Sang , linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH V2] arm64: dts: renesas: r8a77965: Add CAN and CANFD controller nodes Date: Wed, 21 Nov 2018 00:32:52 +0100 Message-Id: <20181120233252.1612-1-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.18.0 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara This patch adds CAN{0,1} and CANFD controller nodes for the R8A77965 SoC. Signed-off-by: Takeshi Kihara Signed-off-by: Marek Vasut Cc: Geert Uytterhoeven Cc: Marc Kleine-Budde Cc: Rob Herring Cc: Simon Horman Cc: Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Acked-by: Wolfram Sang --- V2: Squash the CAN and CANFD addition patches together. --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 51 ++++++++++++++++++++++- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 3a958fb25245..1c86e6f4dc71 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -907,13 +907,60 @@ }; can0: can@e6c30000 { + compatible = "renesas,can-r8a77965", + "renesas,rcar-gen3-can"; reg = <0 0xe6c30000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A77965_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; }; can1: can@e6c38000 { + compatible = "renesas,can-r8a77965", + "renesas,rcar-gen3-can"; reg = <0 0xe6c38000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A77965_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a77965-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77965_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; }; pwm0: pwm@e6e30000 {