| Message ID | 20181129130559.66732-2-chris.brandt@renesas.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Simon Horman |
| Headers | show |
| Series | Add Initial Device Tree for RZ/A2 | expand |
On Thu, Nov 29, 2018 at 08:05:58AM -0500, Chris Brandt wrote: > Basic support for the RZ/A2 (R7S9210) SoC. > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > --- > arch/arm/boot/dts/r7s9210.dtsi | 211 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 211 insertions(+) > create mode 100644 arch/arm/boot/dts/r7s9210.dtsi > > diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi > new file mode 100644 > index 000000000000..3c5373a5c7d2 > --- /dev/null > +++ b/arch/arm/boot/dts/r7s9210.dtsi > @@ -0,0 +1,211 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for the R7S9210 SoC > + * > + * Copyright (C) 2018 Renesas Electronics Corporation > + * > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/r7s9210-cpg-mssr.h> > + > +/ { > + compatible = "renesas,r7s9210"; > + interrupt-parent = <&gic>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + bsid: chipid@fcfe8004 { > + compatible = "renesas,bsid"; > + reg = <0xfcfe8004 4>; > + }; > + > + clocks { > + ranges; > + #address-cells = <1>; > + #size-cells = <1>; > + > + /* External clocks */ > + extal_clk: extal { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + /* Value must be set by board */ > + clock-frequency = <0>; > + }; > + > + rtc_x1_clk: rtc_x1 { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + /* If clk present, value (32678) must be set by board */ > + clock-frequency = <0>; > + }; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + reg = <0>; > + clock-frequency = <528000000>; > + next-level-cache = <&L2>; > + }; > + }; > + > + gic: interrupt-controller@e8221000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0xe8221000 0x1000>, > + <0xe8222000 0x1000>; > + }; > + > + L2: cache-controller@1f003000 { > + compatible = "arm,pl310-cache"; > + reg = <0x1f003000 0x1000>; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + arm,early-bresp-disable; > + arm,full-line-zero-disable; > + cache-unified; > + cache-level = <2>; > + }; > + > + cpg: clock-controller@fcfe0020 { > + compatible = "renesas,r7s9210-cpg-mssr"; > + reg = <0xfcfe0010 0x455>; There is a discrepancy here between the base address, fcfe0020 and the start address of the register range, 0xfcfe0010. > + clocks = <&extal_clk>; > + clock-names = "extal"; > + #clock-cells = <2>; > + #power-domain-cells = <0>; > + #reset-cells = <1>; > + }; > + > + ostm0: timer@e803b000 { > + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; > + reg = <0xe803b000 0x30>; Its not clear to me why the size of the register range is 0x30. > + interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; > + clocks = <&cpg CPG_MOD 36>; > + clock-names = "ostm0"; > + power-domains = <&cpg>; > + status = "disabled"; > + }; > + > + ostm1: timer@e803c000 { > + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; > + reg = <0xe803c000 0x30>; > + interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; > + clocks = <&cpg CPG_MOD 35>; > + clock-names = "ostm1"; > + power-domains = <&cpg>; > + status = "disabled"; > + }; > + > + ostm2: timer@e803d000 { > + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; > + reg = <0xe803d000 0x30>; > + interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>; > + clocks = <&cpg CPG_MOD 34>; > + clock-names = "ostm2"; > + power-domains = <&cpg>; > + status = "disabled"; > + }; > + > + wdt: watchdog@fcfe7000 { > + compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt"; > + reg = <0xfcfe7000 0x26>; > + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_CORE R7S9210_CLK_P0>; > + }; > + > + pinctrl: pin-controller@fcffe000 { > + compatible = "renesas,r7s9210-pinctrl"; > + reg = <0xfcffe000 0x1000>; > + > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pinctrl 0 0 176>; > + }; > + > + scif0: serial@e8007000 { > + compatible = "renesas,scif-r7s9210"; > + reg = <0xe8007000 18>; > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; > + clocks = <&cpg CPG_MOD 47>; > + clock-names = "fck"; > + power-domains = <&cpg>; > + status = "disabled"; > + }; > + > + scif1: serial@e8007800 { > + compatible = "renesas,scif-r7s9210"; > + reg = <0xe8007800 18>; > + interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; > + clocks = <&cpg CPG_MOD 46>; > + clock-names = "fck"; > + power-domains = <&cpg>; > + status = "disabled"; > + }; > + > + scif2: serial@e8008000 { > + compatible = "renesas,scif-r7s9210"; > + reg = <0xe8008000 18>; > + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; > + clocks = <&cpg CPG_MOD 45>; > + clock-names = "fck"; > + power-domains = <&cpg>; > + status = "disabled"; > + }; > + > + scif3: serial@e8008800 { > + compatible = "renesas,scif-r7s9210"; > + reg = <0xe8008800 18>; > + interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; > + clocks = <&cpg CPG_MOD 44>; > + clock-names = "fck"; > + power-domains = <&cpg>; > + status = "disabled"; > + }; > + > + scif4: serial@e8009000 { > + compatible = "renesas,scif-r7s9210"; > + reg = <0xe8009000 18>; > + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; > + clocks = <&cpg CPG_MOD 43>; > + clock-names = "fck"; > + power-domains = <&cpg>; > + status = "disabled"; > + }; > +}; > -- > 2.16.1 >
Hi Simon, On Friday, November 30, 2018, Simon Horman wrote: > > + cpg: clock-controller@fcfe0020 { > > + compatible = "renesas,r7s9210-cpg-mssr"; > > + reg = <0xfcfe0010 0x455>; > > There is a discrepancy here between the base address, fcfe0020 > and the start address of the register range, 0xfcfe0010. Good catch! Thank you. > > + ostm0: timer@e803b000 { > > + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; > > + reg = <0xe803b000 0x30>; > > > Its not clear to me why the size of the register range is 0x30. Because when reviewing the bindings docs, I was putting in 'exact' values, but Geert said "those are ugly, just round up to make it look nicer". So instead of 0x21, I put 0x30. You know...the standard answer: Throw Geert under the bus ;) Chris
On Fri, Nov 30, 2018 at 12:04:57PM +0000, Chris Brandt wrote: > Hi Simon, > > > On Friday, November 30, 2018, Simon Horman wrote: > > > + cpg: clock-controller@fcfe0020 { > > > + compatible = "renesas,r7s9210-cpg-mssr"; > > > + reg = <0xfcfe0010 0x455>; > > > > There is a discrepancy here between the base address, fcfe0020 > > and the start address of the register range, 0xfcfe0010. > > Good catch! Thank you. > > > > > + ostm0: timer@e803b000 { > > > + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; > > > + reg = <0xe803b000 0x30>; > > > > > > Its not clear to me why the size of the register range is 0x30. > > Because when reviewing the bindings docs, I was putting in 'exact' > values, but Geert said "those are ugly, just round up to make it look > nicer". > So instead of 0x21, I put 0x30. > > You know...the standard answer: Throw Geert under the bus ;) Lets leave 0x30 :)
Hi Simon, On Fri, Nov 30, 2018 at 1:23 PM Simon Horman <horms@verge.net.au> wrote: > On Fri, Nov 30, 2018 at 12:04:57PM +0000, Chris Brandt wrote: > > On Friday, November 30, 2018, Simon Horman wrote: > > > > + ostm0: timer@e803b000 { > > > > + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; > > > > + reg = <0xe803b000 0x30>; > > > > > > > > > Its not clear to me why the size of the register range is 0x30. > > > > Because when reviewing the bindings docs, I was putting in 'exact' > > values, but Geert said "those are ugly, just round up to make it look > > nicer". > > So instead of 0x21, I put 0x30. > > > > You know...the standard answer: Throw Geert under the bus ;) > > Lets leave 0x30 :) Pfew... BTW, I'd be surprised the hardware address decoder would route all addresses in the range 0xe803b000..0xe803b02f to the OSTM. 0xe803b000..0xe803b03f sounds more logical to me, as it requires less gates. But hey, who said hardware designers are logical? ;-) Gr{oetje,eeting}s, Geert
From: Geert Uytterhoeven [mailto:geert@linux-m68k.org] Sent: Friday, November 30, 2018 11:03 AM > BTW, I'd be surprised the hardware address decoder would route all > addresses in the range 0xe803b000..0xe803b02f to the OSTM. > 0xe803b000..0xe803b03f sounds more logical to me, as it requires less > gates. Gates??? I thought everything was magical RTL now a days??? Chris
Hi Chris, On Thu, Nov 29, 2018 at 2:07 PM Chris Brandt <chris.brandt@renesas.com> wrote: > Basic support for the RZ/A2 (R7S9210) SoC. > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Thanks for your patch! > --- /dev/null > +++ b/arch/arm/boot/dts/r7s9210.dtsi > @@ -0,0 +1,211 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for the R7S9210 SoC > + * > + * Copyright (C) 2018 Renesas Electronics Corporation > + * > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/r7s9210-cpg-mssr.h> > + > +/ { > + clocks { Please remove the clocks subnode. These days clocks live at the root node. > + gic: interrupt-controller@e8221000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0xe8221000 0x1000>, > + <0xe8222000 0x1000>; > + }; > + > + L2: cache-controller@1f003000 { Please sort nodes by address (per group of devices). > + compatible = "arm,pl310-cache"; > + reg = <0x1f003000 0x1000>; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + arm,early-bresp-disable; > + arm,full-line-zero-disable; > + cache-unified; > + cache-level = <2>; > + }; > + > + cpg: clock-controller@fcfe0020 { fcfe0010, as pointed out by Simon. > + compatible = "renesas,r7s9210-cpg-mssr"; > + reg = <0xfcfe0010 0x455>; > + clocks = <&extal_clk>; > + clock-names = "extal"; > + #clock-cells = <2>; > + #power-domain-cells = <0>; > + #reset-cells = <1>; Note that resets are not yet supported by the driver. But probably they will use #reset-cells = <1>, if ever implemented. > + }; > + > + ostm0: timer@e803b000 { > + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; > + reg = <0xe803b000 0x30>; > + interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; > + clocks = <&cpg CPG_MOD 36>; > + clock-names = "ostm0"; The clock-names property is not documented in the DT bindings. Moreover, using different names for the clock inputs of the different channels is strange. > + scif0: serial@e8007000 { > + compatible = "renesas,scif-r7s9210"; > + reg = <0xe8007000 18>; 0x18 (for all scif instances) Gr{oetje,eeting}s, Geert
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi new file mode 100644 index 000000000000..3c5373a5c7d2 --- /dev/null +++ b/arch/arm/boot/dts/r7s9210.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R7S9210 SoC + * + * Copyright (C) 2018 Renesas Electronics Corporation + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r7s9210-cpg-mssr.h> + +/ { + compatible = "renesas,r7s9210"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + bsid: chipid@fcfe8004 { + compatible = "renesas,bsid"; + reg = <0xfcfe8004 4>; + }; + + clocks { + ranges; + #address-cells = <1>; + #size-cells = <1>; + + /* External clocks */ + extal_clk: extal { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* Value must be set by board */ + clock-frequency = <0>; + }; + + rtc_x1_clk: rtc_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value (32678) must be set by board */ + clock-frequency = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clock-frequency = <528000000>; + next-level-cache = <&L2>; + }; + }; + + gic: interrupt-controller@e8221000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xe8221000 0x1000>, + <0xe8222000 0x1000>; + }; + + L2: cache-controller@1f003000 { + compatible = "arm,pl310-cache"; + reg = <0x1f003000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + arm,early-bresp-disable; + arm,full-line-zero-disable; + cache-unified; + cache-level = <2>; + }; + + cpg: clock-controller@fcfe0020 { + compatible = "renesas,r7s9210-cpg-mssr"; + reg = <0xfcfe0010 0x455>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + ostm0: timer@e803b000 { + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; + reg = <0xe803b000 0x30>; + interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD 36>; + clock-names = "ostm0"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm1: timer@e803c000 { + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; + reg = <0xe803c000 0x30>; + interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD 35>; + clock-names = "ostm1"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm2: timer@e803d000 { + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; + reg = <0xe803d000 0x30>; + interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD 34>; + clock-names = "ostm2"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt: watchdog@fcfe7000 { + compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt"; + reg = <0xfcfe7000 0x26>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_CORE R7S9210_CLK_P0>; + }; + + pinctrl: pin-controller@fcffe000 { + compatible = "renesas,r7s9210-pinctrl"; + reg = <0xfcffe000 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 176>; + }; + + scif0: serial@e8007000 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8007000 18>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 47>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif1: serial@e8007800 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8007800 18>; + interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 46>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif2: serial@e8008000 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8008000 18>; + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 45>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif3: serial@e8008800 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8008800 18>; + interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 44>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif4: serial@e8009000 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8009000 18>; + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 43>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; +};
Basic support for the RZ/A2 (R7S9210) SoC. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> --- arch/arm/boot/dts/r7s9210.dtsi | 211 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 211 insertions(+) create mode 100644 arch/arm/boot/dts/r7s9210.dtsi