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[86.49.110.70]) by smtp.gmail.com with ESMTPSA id w18sm10432692wru.24.2019.03.21.19.38.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Mar 2019 19:38:56 -0700 (PDT) From: marek.vasut@gmail.com To: linux-pci@vger.kernel.org Cc: Marek Vasut , Geert Uytterhoeven , Phil Edworthy , Simon Horman , Wolfram Sang , linux-renesas-soc@vger.kernel.org Subject: [PATCH V2 6/6] PCI: rcar: Allow 64bit MSI addresses Date: Fri, 22 Mar 2019 03:38:44 +0100 Message-Id: <20190322023844.18574-6-marek.vasut@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190322023844.18574-1-marek.vasut@gmail.com> References: <20190322023844.18574-1-marek.vasut@gmail.com> MIME-Version: 1.0 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Marek Vasut The MSI address can be 64bit. Switch the data type used to hold the result of virt_to_phys() to phys_addr_t to reflect its properties correctly and program the top 32bits of PA into PCIEMSIAUR. Signed-off-by: Marek Vasut Cc: Geert Uytterhoeven Cc: Phil Edworthy Cc: Simon Horman Cc: Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org To: linux-pci@vger.kernel.org Reviewed-by: Geert Uytterhoeven --- V2: - s/it's/its/ in commit message - Add R-B from Geert --- drivers/pci/controller/pcie-rcar.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c index 989b7b73ed61..75ac83f21035 100644 --- a/drivers/pci/controller/pcie-rcar.c +++ b/drivers/pci/controller/pcie-rcar.c @@ -889,7 +889,7 @@ static int rcar_pcie_enable_msi(struct rcar_pcie *pcie) { struct device *dev = pcie->dev; struct rcar_msi *msi = &pcie->msi; - unsigned long base; + phys_addr_t base; int err, i; mutex_init(&msi->lock); @@ -931,7 +931,7 @@ static int rcar_pcie_enable_msi(struct rcar_pcie *pcie) base = virt_to_phys((void *)msi->pages); rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR); - rcar_pci_write_reg(pcie, 0, PCIEMSIAUR); + rcar_pci_write_reg(pcie, base >> 32, PCIEMSIAUR); /* enable all MSI interrupts */ rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);