From patchwork Tue Apr 30 13:23:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 10923669 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DC2DE92A for ; Tue, 30 Apr 2019 13:33:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CC93728358 for ; Tue, 30 Apr 2019 13:33:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BFE332881A; Tue, 30 Apr 2019 13:33:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 67E432881A for ; Tue, 30 Apr 2019 13:33:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726858AbfD3Ndd (ORCPT ); Tue, 30 Apr 2019 09:33:33 -0400 Received: from pbmsgap02.intersil.com ([192.157.179.202]:40566 "EHLO pbmsgap02.intersil.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726428AbfD3Ndc (ORCPT ); Tue, 30 Apr 2019 09:33:32 -0400 Received: from pps.filterd (pbmsgap02.intersil.com [127.0.0.1]) by pbmsgap02.intersil.com (8.16.0.27/8.16.0.27) with SMTP id x3UDNK9F032150; Tue, 30 Apr 2019 09:23:25 -0400 Received: from pbmxdp02.intersil.corp (pbmxdp02.pb.intersil.com [132.158.200.223]) by pbmsgap02.intersil.com with ESMTP id 2s4h8d2csj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 30 Apr 2019 09:23:25 -0400 Received: from pbmxdp03.intersil.corp (132.158.200.224) by pbmxdp02.intersil.corp (132.158.200.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.1531.3; Tue, 30 Apr 2019 09:23:24 -0400 Received: from localhost.localdomain (132.158.202.108) by pbmxdp03.intersil.corp (132.158.200.224) with Microsoft SMTP Server id 15.1.1531.3 via Frontend Transport; Tue, 30 Apr 2019 09:23:23 -0400 From: Chris Brandt To: Simon Horman , Rob Herring , "Mark Rutland" CC: , , , Chris Brandt Subject: [PATCH 5/7] ARM: dts: r7s9210: Add SDHI support Date: Tue, 30 Apr 2019 08:23:07 -0500 Message-ID: <20190430132309.12473-6-chris.brandt@renesas.com> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20190430132309.12473-1-chris.brandt@renesas.com> References: <20190430132309.12473-1-chris.brandt@renesas.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-04-30_06:,, signatures=0 X-Proofpoint-Spam-Details: rule=junk_notspam policy=junk score=0 suspectscore=2 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=842 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1904300086 X-Proofpoint-Spam-Reason: mlx Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add SDHI support for the R7S9210 (RZ/A2) SoC. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r7s9210.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi index 1cd982c9920f..2eaa5eeba509 100644 --- a/arch/arm/boot/dts/r7s9210.dtsi +++ b/arch/arm/boot/dts/r7s9210.dtsi @@ -322,6 +322,30 @@ status = "disabled"; }; + sdhi0: sd@e8228000 { + compatible = "renesas,sdhi-r7s9210"; + reg = <0xe8228000 0x8c0>; + interrupts = ; + clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 102>; + clock-names = "core", "cd"; + power-domains = <&cpg>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi1: sd@e822a000 { + compatible = "renesas,sdhi-r7s9210"; + reg = <0xe822a000 0x8c0>; + interrupts = ; + clocks = <&cpg CPG_MOD 101>, <&cpg CPG_MOD 100>; + clock-names = "core", "cd"; + power-domains = <&cpg>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + gic: interrupt-controller@e8221000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;