| Message ID | 20190514145605.19112-5-chris.brandt@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | usb: Add host and device support for RZ/A2 | expand |
On Tue, 14 May 2019 09:55:54 -0500, Chris Brandt wrote: > Document the USB_X1 input and add clock-names to identify > functional and USB_X1 clocks. > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > --- > v3: > * added clock names > v2: > * removed 'use_usb_x1' option > * document that 'usb_x1' clock node will be detected to determine if > 48MHz clock exists > --- > Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > Reviewed-by: Rob Herring <robh@kernel.org>
Hi Chris-san, > From: Chris Brandt, Sent: Tuesday, May 14, 2019 11:56 PM > > Document the USB_X1 input and add clock-names to identify > functional and USB_X1 clocks. > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Thank you for the patch! Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Best regards, Yoshihiro Shimoda
On Tue, May 14, 2019 at 4:57 PM Chris Brandt <chris.brandt@renesas.com> wrote: > Document the USB_X1 input and add clock-names to identify > functional and USB_X1 clocks. > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt > +++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt > @@ -28,7 +28,11 @@ Required properties: > followed by the generic version. > > - reg: offset and length of the partial USB 2.0 Host register block. > -- clocks: clock phandle and specifier pair(s). > +- clocks: clock phandle and specifier pair(s). For SoCs that have a separate > + dedicated USB_X1 input for the PLL, that is also listed. > +- clock-names: Name of the clocks. The functional clock shall be called "fclk" Names? > + and USB_X1 shall be called "usb_x1". If only one clock is listed, > + this property is not required. > - #phy-cells: see phy-bindings.txt in the same directory, must be <1> (and > using <0> is deprecated). Gr{oetje,eeting}s, Geert
On Tue, May 14, 2019 at 09:55:54AM -0500, Chris Brandt wrote: > Document the USB_X1 input and add clock-names to identify > functional and USB_X1 clocks. > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Hello! On 15.05.2019 10:35, Geert Uytterhoeven wrote: >> Document the USB_X1 input and add clock-names to identify >> functional and USB_X1 clocks. >> >> Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > >> --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt >> +++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt >> @@ -28,7 +28,11 @@ Required properties: >> followed by the generic version. >> >> - reg: offset and length of the partial USB 2.0 Host register block. >> -- clocks: clock phandle and specifier pair(s). >> +- clocks: clock phandle and specifier pair(s). For SoCs that have a separate >> + dedicated USB_X1 input for the PLL, that is also listed. >> +- clock-names: Name of the clocks. The functional clock shall be called "fclk" > > Names? And I think the module clock name was "fck", not "fclk"... [...] > Gr{oetje,eeting}s, > > Geert MBR, Sergei
Hi Sergei, On Wed, May 15, 2019 at 10:39 AM Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > On 15.05.2019 10:35, Geert Uytterhoeven wrote: > >> Document the USB_X1 input and add clock-names to identify > >> functional and USB_X1 clocks. > >> > >> Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > >> --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt > >> +++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt > >> @@ -28,7 +28,11 @@ Required properties: > >> followed by the generic version. > >> > >> - reg: offset and length of the partial USB 2.0 Host register block. > >> -- clocks: clock phandle and specifier pair(s). > >> +- clocks: clock phandle and specifier pair(s). For SoCs that have a separate > >> + dedicated USB_X1 input for the PLL, that is also listed. > >> +- clock-names: Name of the clocks. The functional clock shall be called "fclk" > > > > Names? > > And I think the module clock name was "fck", not "fclk"... Indeed, sorry for missing that. Gr{oetje,eeting}s, Geert
diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt index d46188f450bf..ca8a831d4273 100644 --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt +++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt @@ -28,7 +28,11 @@ Required properties: followed by the generic version. - reg: offset and length of the partial USB 2.0 Host register block. -- clocks: clock phandle and specifier pair(s). +- clocks: clock phandle and specifier pair(s). For SoCs that have a separate + dedicated USB_X1 input for the PLL, that is also listed. +- clock-names: Name of the clocks. The functional clock shall be called "fclk" + and USB_X1 shall be called "usb_x1". If only one clock is listed, + this property is not required. - #phy-cells: see phy-bindings.txt in the same directory, must be <1> (and using <0> is deprecated).
Document the USB_X1 input and add clock-names to identify functional and USB_X1 clocks. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> --- v3: * added clock names v2: * removed 'use_usb_x1' option * document that 'usb_x1' clock node will be detected to determine if 48MHz clock exists --- Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)