From patchwork Sun Dec 20 19:50:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Pinchart X-Patchwork-Id: 11983983 X-Patchwork-Delegate: kieran@bingham.xyz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4E51C4361B for ; Sun, 20 Dec 2020 19:54:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AC35922AAD for ; Sun, 20 Dec 2020 19:54:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726593AbgLTTy0 (ORCPT ); Sun, 20 Dec 2020 14:54:26 -0500 Received: from perceval.ideasonboard.com ([213.167.242.64]:53110 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726584AbgLTTy0 (ORCPT ); Sun, 20 Dec 2020 14:54:26 -0500 Received: from pendragon.lan (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id E7D8045E; Sun, 20 Dec 2020 20:50:18 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1608493819; bh=r500VogUG2STcIuAc/UQqHpr6ZmYpBHy/1ydmJVZ+iE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aDLO70XhaTfutHDLgfyVxG0/2ew1kZyGDSvijuVuts5lf4D/LIzKnagsDOBb838Uf jPrS2o1qkz/YHbEsLNAQv2wLpzHYG8ckmph0Z862k12knCNkUJNf/UKKX65t+whUdC nuWtLGbHKgxtAvBzqBtETBQfNZWNJHc72AczDodU= From: Laurent Pinchart To: dri-devel@lists.freedesktop.org Cc: Rob Herring , Sandy Huang , linux-renesas-soc@vger.kernel.org, Chen-Yu Tsai , Maxime Ripard , Mark Yao , Philipp Zabel Subject: [PATCH v2 1/6] dt-bindings: display: bridge: Add YAML schema for Synopsys DW-HDMI Date: Sun, 20 Dec 2020 21:50:00 +0200 Message-Id: <20201220195005.26438-2-laurent.pinchart+renesas@ideasonboard.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201220195005.26438-1-laurent.pinchart+renesas@ideasonboard.com> References: <20201220195005.26438-1-laurent.pinchart+renesas@ideasonboard.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add a .yaml schema containing the common properties for the Synopsys DesignWare HDMI TX controller. This isn't a full device tree binding specification, but is meant to be referenced by platform-specific bindings for the IP core. Signed-off-by: Laurent Pinchart Reviewed-by: Philipp Zabel --- Changes since v1: - Add default to reg-io-width property - Add additionalProperties - Rebase on top of OF graph schema, dropped redundant properties - Drop cec clock as it's device-specific - Increase max clocks to 5 to accommodate the Rockchip DW-HDMI --- .../display/bridge/synopsys,dw-hdmi.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml new file mode 100644 index 000000000000..96c4bc06dbe7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Properties for Synopsys DesignWare HDMI TX Controller + +maintainers: + - Laurent Pinchart + +description: | + This document defines device tree properties for the Synopsys DesignWare HDMI + TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree + binding specification by itself but is meant to be referenced by device tree + bindings for the platform-specific integrations of the DWC HDMI TX. + + When referenced from platform device tree bindings the properties defined in + this document are defined as follows. The platform device tree bindings are + responsible for defining whether each property is required or optional. + +properties: + reg: + maxItems: 1 + + reg-io-width: + description: + Width (in bytes) of the registers specified by the reg property. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [1, 4] + default: 1 + + clocks: + minItems: 2 + maxItems: 5 + items: + - description: The bus clock for either AHB and APB + - description: The internal register configuration clock + additionalItems: true + + clock-names: + minItems: 2 + maxItems: 5 + items: + - const: iahb + - const: isfr + additionalItems: true + + interrupts: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + +additionalProperties: true + +...