| Message ID | 20210616132641.29087-2-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | pinctrl: Add RZ/G2L pin and gpio driver | expand |
On Wed, 16 Jun 2021 14:26:39 +0100, Lad Prabhakar wrote: > Add device tree binding documentation and header file for Renesas > RZ/G2L pinctrl. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > .../pinctrl/renesas,rzg2l-pinctrl.yaml | 121 ++++++++++++++++++ > include/dt-bindings/pinctrl/pinctrl-rzg2l.h | 16 +++ > 2 files changed, 137 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > create mode 100644 include/dt-bindings/pinctrl/pinctrl-rzg2l.h > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.example.dts:20:18: fatal error: dt-bindings/clock/r9a07g044-cpg.h: No such file or directory 20 | #include <dt-bindings/clock/r9a07g044-cpg.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1416: dt_binding_check] Error 2 \ndoc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1492923 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Wed, Jun 16, 2021 at 02:26:39PM +0100, Lad Prabhakar wrote: > Add device tree binding documentation and header file for Renesas > RZ/G2L pinctrl. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > .../pinctrl/renesas,rzg2l-pinctrl.yaml | 121 ++++++++++++++++++ > include/dt-bindings/pinctrl/pinctrl-rzg2l.h | 16 +++ > 2 files changed, 137 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > create mode 100644 include/dt-bindings/pinctrl/pinctrl-rzg2l.h > > diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > new file mode 100644 > index 000000000000..e8ab5a0a46b3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > @@ -0,0 +1,121 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L combined Pin and GPIO controller > + > +maintainers: > + - Geert Uytterhoeven <geert+renesas@glider.be> > + > +description: > + The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO > + controller. > + Pin multiplexing and GPIO configuration is performed on a per-pin basis. > + Each port features up to 8 pins, each of them configurable for GPIO function > + (port mode) or in alternate function mode. > + Up to 8 different alternate function modes exist for each single pin. > + > +properties: > + compatible: > + enum: > + - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} > + > + reg: > + maxItems: 1 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 > + description: > + The first cell contains the global GPIO port index, constructed using the > + RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/pinctrl-rzg2l.h> and the > + second cell represents consumer flag as mentioned in ../gpio/gpio.txt > + E.g. "RZG2L_GPIO(39, 1)" for P39_1. > + > + gpio-ranges: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > +additionalProperties: > + anyOf: > + - type: object Define a node name pattern for child nodes to match on rather than using 'additionalProperties'. '-pins$' for example. > + allOf: > + - $ref: pincfg-node.yaml# > + - $ref: pinmux-node.yaml# > + > + description: > + Pin controller client devices use pin configuration subnodes (children > + and grandchildren) for desired pin configuration. > + Client device subnodes use below standard properties. > + > + properties: > + phandle: true > + function: true > + groups: true > + pins: true > + bias-disable: true > + bias-pull-down: true > + bias-pull-up: true > + drive-strength: > + enum: [ 2, 4, 8, 12 ] > + power-source: > + enum: [ 1800, 2500, 3300 ] > + slew-rate: true > + gpio-hog: true > + gpios: true > + input-enable: true > + output-high: true > + output-low: true > + line-name: true > + > + additionalProperties: false > + > +required: > + - compatible > + - reg > + - gpio-controller > + - '#gpio-cells' > + - gpio-ranges > + - clocks > + - power-domains > + - resets > + > +examples: > + - | > + #include <dt-bindings/pinctrl/pinctrl-rzg2l.h> > + #include <dt-bindings/clock/r9a07g044-cpg.h> > + > + pinctrl: pinctrl@11030000 { > + compatible = "renesas,r9a07g044l-pinctrl"; > + reg = <0x11030000 0x10000>; > + > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pinctrl 0 0 392>; > + clocks = <&cpg CPG_MOD R9A07G044_CLK_GPIO>; > + resets = <&cpg R9A07G044_CLK_GPIO>; > + power-domains = <&cpg>; > + > + scif0_pins: scif0 { > + groups = "scif0_data"; > + function = "scif0"; > + }; > + > + sd1-pwr-en-hog { > + gpio-hog; > + gpios = <RZG2L_GPIO(39, 2) 0>; > + output-high; > + line-name = "sd1_pwr_en"; > + }; > + }; > diff --git a/include/dt-bindings/pinctrl/pinctrl-rzg2l.h b/include/dt-bindings/pinctrl/pinctrl-rzg2l.h > new file mode 100644 > index 000000000000..d285d9e8c60a > --- /dev/null > +++ b/include/dt-bindings/pinctrl/pinctrl-rzg2l.h > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * This header provides constants for Renesas RZ/G2{L,LC} pinctrl bindings. > + * > + * Copyright (C) 2021 Renesas Electronics Corp. > + * > + */ > + > +#ifndef __DT_BINDINGS_PINCTRL_RZG2L_H > +#define __DT_BINDINGS_PINCTRL_RZG2L_H > + > +#define RZG2L_PINS_PER_PORT 8 > + > +#define RZG2L_GPIO(port, pos) ((port) * RZG2L_PINS_PER_PORT + (pos)) > + > +#endif /* __DT_BINDINGS_PINCTRL_RZG2L_H */ > -- > 2.17.1
Hi Prabhakar, On Wed, Jun 16, 2021 at 3:27 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add device tree binding documentation and header file for Renesas > RZ/G2L pinctrl. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > @@ -0,0 +1,121 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L combined Pin and GPIO controller > + > +maintainers: > + - Geert Uytterhoeven <geert+renesas@glider.be> > + > +description: > + The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO > + controller. > + Pin multiplexing and GPIO configuration is performed on a per-pin basis. > + Each port features up to 8 pins, each of them configurable for GPIO function > + (port mode) or in alternate function mode. > + Up to 8 different alternate function modes exist for each single pin. > + > +properties: > + compatible: > + enum: > + - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} > + > + reg: > + maxItems: 1 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 > + description: > + The first cell contains the global GPIO port index, constructed using the > + RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/pinctrl-rzg2l.h> and the <dt-bindings/pinctrl/rzg2l-pinctrl.h>, for consistency with other Renesas header files? > + second cell represents consumer flag as mentioned in ../gpio/gpio.txt > + E.g. "RZG2L_GPIO(39, 1)" for P39_1. > + > + gpio-ranges: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > +additionalProperties: > + anyOf: > + - type: object > + allOf: > + - $ref: pincfg-node.yaml# > + - $ref: pinmux-node.yaml# > + > + description: > + Pin controller client devices use pin configuration subnodes (children > + and grandchildren) for desired pin configuration. > + Client device subnodes use below standard properties. > + > + properties: > + phandle: true > + function: true > + groups: true RZ/G2L uses per-pin configuration, and, unlike R-Car, the configuration registers do not have the concept of pin groups. Hence I'm wondering why you are using "function" and "group" properties, and not per-pin "pinmux" properties, like RZ/A2? > + pins: true > + bias-disable: true > + bias-pull-down: true > + bias-pull-up: true > + drive-strength: > + enum: [ 2, 4, 8, 12 ] > + power-source: > + enum: [ 1800, 2500, 3300 ] > + slew-rate: true > + gpio-hog: true > + gpios: true > + input-enable: true > + output-high: true > + output-low: true > + line-name: true > --- /dev/null > +++ b/include/dt-bindings/pinctrl/pinctrl-rzg2l.h include/dt-bindings/pinctrl/rzg2l-pinctrl.h, for consistency? > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * This header provides constants for Renesas RZ/G2{L,LC} pinctrl bindings. > + * > + * Copyright (C) 2021 Renesas Electronics Corp. > + * > + */ > + > +#ifndef __DT_BINDINGS_PINCTRL_RZG2L_H > +#define __DT_BINDINGS_PINCTRL_RZG2L_H __DT_BINDINGS_RZG2L_PINCTRL_H Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml new file mode 100644 index 000000000000..e8ab5a0a46b3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L combined Pin and GPIO controller + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: + The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO + controller. + Pin multiplexing and GPIO configuration is performed on a per-pin basis. + Each port features up to 8 pins, each of them configurable for GPIO function + (port mode) or in alternate function mode. + Up to 8 different alternate function modes exist for each single pin. + +properties: + compatible: + enum: + - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + description: + The first cell contains the global GPIO port index, constructed using the + RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/pinctrl-rzg2l.h> and the + second cell represents consumer flag as mentioned in ../gpio/gpio.txt + E.g. "RZG2L_GPIO(39, 1)" for P39_1. + + gpio-ranges: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + Pin controller client devices use pin configuration subnodes (children + and grandchildren) for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + phandle: true + function: true + groups: true + pins: true + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: + enum: [ 2, 4, 8, 12 ] + power-source: + enum: [ 1800, 2500, 3300 ] + slew-rate: true + gpio-hog: true + gpios: true + input-enable: true + output-high: true + output-low: true + line-name: true + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - clocks + - power-domains + - resets + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-rzg2l.h> + #include <dt-bindings/clock/r9a07g044-cpg.h> + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a07g044l-pinctrl"; + reg = <0x11030000 0x10000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 392>; + clocks = <&cpg CPG_MOD R9A07G044_CLK_GPIO>; + resets = <&cpg R9A07G044_CLK_GPIO>; + power-domains = <&cpg>; + + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + sd1-pwr-en-hog { + gpio-hog; + gpios = <RZG2L_GPIO(39, 2) 0>; + output-high; + line-name = "sd1_pwr_en"; + }; + }; diff --git a/include/dt-bindings/pinctrl/pinctrl-rzg2l.h b/include/dt-bindings/pinctrl/pinctrl-rzg2l.h new file mode 100644 index 000000000000..d285d9e8c60a --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-rzg2l.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G2{L,LC} pinctrl bindings. + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_PINCTRL_RZG2L_H +#define __DT_BINDINGS_PINCTRL_RZG2L_H + +#define RZG2L_PINS_PER_PORT 8 + +#define RZG2L_GPIO(port, pos) ((port) * RZG2L_PINS_PER_PORT + (pos)) + +#endif /* __DT_BINDINGS_PINCTRL_RZG2L_H */