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mx.microsoft.com 1; spf=pass smtp.mailfrom=windriver.com; dmarc=pass action=none header.from=windriver.com; dkim=pass header.d=windriver.com; arc=none Authentication-Results: glider.be; dkim=none (message not signed) header.d=none;glider.be; dmarc=none action=none header.from=windriver.com; Received: from PH0PR11MB5191.namprd11.prod.outlook.com (2603:10b6:510:3e::24) by PH0PR11MB5207.namprd11.prod.outlook.com (2603:10b6:510:32::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.15; Tue, 19 Oct 2021 09:59:40 +0000 Received: from PH0PR11MB5191.namprd11.prod.outlook.com ([fe80::c11a:b99e:67ce:4a14]) by PH0PR11MB5191.namprd11.prod.outlook.com ([fe80::c11a:b99e:67ce:4a14%8]) with mapi id 15.20.4608.018; Tue, 19 Oct 2021 09:59:40 +0000 From: Meng Li To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, marek.vasut+renesas@gmail.com, yoshihiro.shimoda.uh@renesas.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, lgirdwood@gmail.com, broonie@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, meng.li@windriver.com Subject: [PATCH] pci: pcie-rcar: add regulators support Date: Tue, 19 Oct 2021 17:58:58 +0800 Message-Id: <20211019095858.21316-1-Meng.Li@windriver.com> X-Mailer: git-send-email 2.17.1 X-ClientProxiedBy: HK2PR02CA0175.apcprd02.prod.outlook.com (2603:1096:201:21::11) To PH0PR11MB5191.namprd11.prod.outlook.com (2603:10b6:510:3e::24) MIME-Version: 1.0 Received: from pek-mli1-d2.wrs.com (60.247.85.82) by HK2PR02CA0175.apcprd02.prod.outlook.com (2603:1096:201:21::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.16 via Frontend Transport; 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Signed-off-by: Meng Li --- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 47 +++++++++++++++++ drivers/pci/controller/pcie-rcar-host.c | 64 ++++++++++++++++++++++++ 2 files changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 8986a7e6e099..82e463c32a37 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -50,6 +50,25 @@ startup-delay-us = <70000>; enable-active-high; }; + + mpcie_3v3: regulator-mpcie_3v3 { + compatible = "regulator-fixed"; + regulator-name = "mPCIe 3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio_exp_77 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + mpcie_1v8: regulator-mpcie_1v8 { + compatible = "regulator-fixed"; + regulator-name = "mPCIe 1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio_exp_77 15 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + enable-active-high; + }; }; &can0 { @@ -241,6 +260,31 @@ interrupt-controller; interrupt-parent = <&gpio5>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + + mpcie_wake { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "mPCIe WAKE#"; + }; + mpcie_wdisable { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "mPCIe W_DISABLE"; + }; + mpcie_clreq { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + input; + line-name = "mPCIe CLKREQ#"; + }; + mpcie_ovc { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + input; + line-name = "mPCIe OVC"; + }; }; }; @@ -259,6 +303,9 @@ &pciec1 { status = "okay"; + + pcie3v3-supply = <&mpcie_3v3>; + pcie1v8-supply = <&mpcie_1v8>; }; &pfc { diff --git a/drivers/pci/controller/pcie-rcar-host.c b/drivers/pci/controller/pcie-rcar-host.c index cdc0963f154e..bf1e4007876e 100644 --- a/drivers/pci/controller/pcie-rcar-host.c +++ b/drivers/pci/controller/pcie-rcar-host.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -54,6 +55,8 @@ struct rcar_pcie_host { struct rcar_pcie pcie; struct phy *phy; struct clk *bus_clk; + struct regulator *pcie3v3; /* 3.3V power supply */ + struct regulator *pcie1v8; /* 1.8V power supply */ struct rcar_msi msi; int (*phy_init_fn)(struct rcar_pcie_host *host); }; @@ -893,6 +896,36 @@ static const struct of_device_id rcar_pcie_of_match[] = { {}, }; +static int rcar_pcie_set_vpcie(struct rcar_pcie_host *host) +{ + struct device *dev = host->pcie.dev; + int err; + + if (!IS_ERR(host->pcie3v3)) { + err = regulator_enable(host->pcie3v3); + if (err) { + dev_err(dev, "fail to enable vpcie3v3 regulator\n"); + goto err_out; + } + } + + if (!IS_ERR(host->pcie1v8)) { + err = regulator_enable(host->pcie1v8); + if (err) { + dev_err(dev, "fail to enable vpcie1v8 regulator\n"); + goto err_disable_3v3; + } + } + + return 0; + +err_disable_3v3: + if (!IS_ERR(host->pcie3v3)) + regulator_disable(host->pcie3v3); +err_out: + return err; +} + static int rcar_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -911,6 +944,31 @@ static int rcar_pcie_probe(struct platform_device *pdev) pcie->dev = dev; platform_set_drvdata(pdev, host); + host->pcie3v3 = devm_regulator_get_optional(dev, "pcie3v3"); + if (IS_ERR(host->pcie3v3)) { + if (PTR_ERR(host->pcie3v3) == -EPROBE_DEFER) { + pci_free_host_bridge(bridge); + return -EPROBE_DEFER; + } + dev_info(dev, "no pcie3v3 regulator found\n"); + } + + host->pcie1v8 = devm_regulator_get_optional(dev, "pcie1v8"); + if (IS_ERR(host->pcie1v8)) { + if (PTR_ERR(host->pcie1v8) == -EPROBE_DEFER) { + pci_free_host_bridge(bridge); + return -EPROBE_DEFER; + } + dev_info(dev, "no pcie1v8 regulator found\n"); + } + + err = rcar_pcie_set_vpcie(host); + if (err) { + dev_err(dev, "failed to set pcie regulators\n"); + pci_free_host_bridge(bridge); + return err; + } + pm_runtime_enable(pcie->dev); err = pm_runtime_get_sync(pcie->dev); if (err < 0) { @@ -985,6 +1043,12 @@ static int rcar_pcie_probe(struct platform_device *pdev) irq_dispose_mapping(host->msi.irq1); err_pm_put: + if(!IS_ERR(host->pcie3v3)) + if (regulator_is_enabled(host->pcie3v3)) + regulator_disable(host->pcie3v3); + if(!IS_ERR(host->pcie1v8)) + if (regulator_is_enabled(host->pcie1v8)) + regulator_disable(host->pcie1v8); pm_runtime_put(dev); pm_runtime_disable(dev);