| Message ID | 20211121234906.9602-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | [v2] arm64: dts: renesas: rzg2l-smarc-som: Enable serial NOR flash | expand |
On 22.11.2021 2:49, Lad Prabhakar wrote: > Enable mt25qu512a flash connected to QSPI0. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > v1->v2 > -> Renamed qspi_pins0 to qspi0_pins > --- > .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 40 +++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > index 7e84a29dddfa..aef1b8736732 100644 > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > @@ -178,6 +178,18 @@ > line-name = "gpio_sd0_pwr_en"; > }; > > + qspi0_pins: qspi0 { > + qspi0-data { > + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; > + power-source = <1800>; Hrm, sorry for more nitpicking... Why 2 spaces before =? > + }; > + > + qspi0-ctrl { > + pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; > + power-source = <1800>; Here as well... > + }; > + }; > + > /* > * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] > * The below switch logic can be used to select the device between [...] MBR, Sergey
Hi Sergey, Thank you for the review. On Mon, Nov 22, 2021 at 8:06 PM Sergey Shtylyov <s.shtylyov@omp.ru> wrote: > > On 22.11.2021 2:49, Lad Prabhakar wrote: > > > Enable mt25qu512a flash connected to QSPI0. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > v1->v2 > > -> Renamed qspi_pins0 to qspi0_pins > > --- > > .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 40 +++++++++++++++++++ > > 1 file changed, 40 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > > index 7e84a29dddfa..aef1b8736732 100644 > > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > > @@ -178,6 +178,18 @@ > > line-name = "gpio_sd0_pwr_en"; > > }; > > > > + qspi0_pins: qspi0 { > > + qspi0-data { > > + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; > > + power-source = <1800>; > > Hrm, sorry for more nitpicking... Why 2 spaces before =? > Argh my bad... > > + }; > > + > > + qspi0-ctrl { > > + pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; > > + power-source = <1800>; > > Here as well... > .. will fix that. Cheers, Prabhakar > > + }; > > + }; > > + > > /* > > * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] > > * The below switch logic can be used to select the device between > [...] > > MBR, Sergey >
On Mon, Nov 22, 2021 at 12:49 AM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Enable mt25qu512a flash connected to QSPI0. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.17... > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > @@ -178,6 +178,18 @@ > line-name = "gpio_sd0_pwr_en"; > }; > > + qspi0_pins: qspi0 { > + qspi0-data { > + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; > + power-source = <1800>; ... with the bogus spaces ... > + }; > + > + qspi0-ctrl { > + pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; > + power-source = <1800>; ... removed. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 7e84a29dddfa..aef1b8736732 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -178,6 +178,18 @@ line-name = "gpio_sd0_pwr_en"; }; + qspi0_pins: qspi0 { + qspi0-data { + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; + power-source = <1800>; + }; + + qspi0-ctrl { + pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; + power-source = <1800>; + }; + }; + /* * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] * The below switch logic can be used to select the device between @@ -243,6 +255,34 @@ }; }; +&sbc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,mt25qu512a", "jedec,spi-nor"; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x00000000 0x2000000>; + read-only; + }; + user@2000000 { + reg = <0x2000000 0x2000000>; + }; + }; + }; +}; + #if SDHI &sdhi0 { pinctrl-0 = <&sdhi0_pins>;