From patchwork Fri Jan 21 01:05:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 12719206 X-Patchwork-Delegate: kieran@bingham.xyz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B156C433F5 for ; Fri, 21 Jan 2022 01:06:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234269AbiAUBGM (ORCPT ); Thu, 20 Jan 2022 20:06:12 -0500 Received: from relmlor1.renesas.com ([210.160.252.171]:11183 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233641AbiAUBGJ (ORCPT ); Thu, 20 Jan 2022 20:06:09 -0500 X-IronPort-AV: E=Sophos;i="5.88,303,1635174000"; d="scan'208";a="107143426" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 21 Jan 2022 10:06:08 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 925BF417762A; Fri, 21 Jan 2022 10:06:05 +0900 (JST) From: Lad Prabhakar To: =?utf-8?q?Niklas_S=C3=B6derlund?= , Jacopo Mondi , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Laurent Pinchart , Sakari Ailus , Hans Verkuil Cc: Geert Uytterhoeven , linux-media@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [RFC PATCH v2 2/4] media: dt-bindings: media: Document RZ/G2L CRU Date: Fri, 21 Jan 2022 01:05:41 +0000 Message-Id: <20220121010543.31385-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220121010543.31385-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220121010543.31385-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Document the CRU block found on Renesas RZ/G2L SoC's. Signed-off-by: Lad Prabhakar --- v1->v2 * Dropped CSI --- .../bindings/media/renesas,rzg2l-cru.yaml | 152 ++++++++++++++++++ 1 file changed, 152 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml new file mode 100644 index 000000000000..a03fc6ef0117 --- /dev/null +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2022 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L Camera Data Receiving Unit (CRU) + +maintainers: + - Lad Prabhakar + +description: + The RZ/G2L Camera Data Receiving Unit (CRU) device provides video input + capabilities for the Renesas RZ/G2L family of devices. + + Depending on the instance the Image Processing input is connected to + external SoC pins or to a CSI-2 receiver. + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,r9a07g044-cru # RZ/G2{L,LC} + - const: renesas,rzg2l-cru + + reg: + maxItems: 1 + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: image_conv + - const: image_conv_err + - const: axi_mst_err + + clocks: + items: + - description: CRU Main clock + - description: CPU Register access clock + - description: CRU image transfer clock + + clock-names: + items: + - const: vclk + - const: pclk + - const: aclk + + power-domains: + maxItems: 1 + + resets: + items: + - description: CRU_PRESETN reset terminal + - description: CRU_ARESETN reset terminal + + reset-names: + items: + - const: presetn + - const: aresetn + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port node, single endpoint describing a parallel input source. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + hsync-active: true + vsync-active: true + bus-width: true + data-shift: true + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port node, describing the RZ/G2L Image Processing module + connected the CSI-2 receiver + + properties: + endpoint@0: + $ref: /schemas/graph.yaml#/properties/endpoint + description: Endpoint connected to CSI2. + + anyOf: + - required: + - endpoint@0 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + +additionalProperties: false + +examples: + # Device node example with CSI-2 + - | + #include + #include + + cru: video@10830000 { + compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru"; + reg = <0x10830000 0x400>; + interrupts = , + , + ; + interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; + clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>, + <&cpg CPG_MOD R9A07G044_CRU_PCLK>, + <&cpg CPG_MOD R9A07G044_CRU_ACLK>; + clock-names = "vclk", "pclk", "aclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_CRU_PRESETN>, + <&cpg R9A07G044_CRU_ARESETN>; + reset-names = "presetn", "aresetn"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + crucsi2: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi2cru>; + }; + }; + }; + };