| Message ID | 20220330154024.112270-13-phil.edworthy@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support | expand |
Hi Phil, On Wed, Mar 30, 2022 at 5:42 PM Phil Edworthy <phil.edworthy@renesas.com> wrote: > Details of the SoC can be found here: > https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Thanks for your patch! > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi > @@ -0,0 +1,99 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/V2M SoC > + * > + * Copyright (C) 2022 Renesas Electronics Corp. > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/r9a09g011-cpg.h> > + > +/ { > + compatible = "renesas,r9a09g011"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ > + extal_clk: extal { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + /* This value must be overridden by the board */ > + clock-frequency = <0>; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a53"; > + reg = <0>; > + device_type = "cpu"; > + clocks = <&cpg CPG_CORE R9A09G011_CA53_CLK>; CPG_MOD? > + }; > + }; > + > + soc: soc { > + compatible = "simple-bus"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + gic: interrupt-controller@82000000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x0 0x82010000 0 0x1000>, > + <0x0 0x82020000 0 0x20000>, > + <0x0 0x82040000 0 0x20000>, > + <0x0 0x82060000 0 0x20000>; > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>; clock-names = "clk"; > + }; > + > + cpg: clock-controller@a3500000 { > + compatible = "renesas,r9a09g011-cpg"; > + reg = <0 0xa3500000 0 0x10000>; Size should be 0x1000, according to the address map. > + clocks = <&extal_clk>; > + clock-names = "extal"; > + #clock-cells = <2>; > + #reset-cells = <1>; > + #power-domain-cells = <0>; > + }; > + > + sys: system-configuration@a3f03000 { > + compatible = "renesas,r9a09g011-sys"; system-controller@a3f03000? Pending acceptance of the DT bindings. > + reg = <0 0xa3f03000 0 0x400>; > + status = "disabled"; I think there is no need to keep this disabled. > + }; > + > + uart0: serial@a4040000 { > + compatible = "renesas,r9a09g011-uart", "renesas,em-uart"; > + reg = <0 0xa4040000 0 0x38>; Register offsets are documented until and including 0x7c, so size should be 0x80 (which matches the address map). > + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>; > + clock-names = "sclk"; > + status = "disabled"; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; > + clocks = <&cpg CPG_MOD R9A09G011_SYC_CNT_CLK>; > + clock-names = "clk"; > + resets = <&cpg R9A09G011_SYC_RST_N>; The three properties above are not document, causing the following "make dtbs_check" error message: arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dtb: timer: 'clock-names', 'clocks', 'resets' do not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/timer/arm,arch_timer.yaml > + }; > +}; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, On 26 April 2022 19:13 Geert Uytterhoeven wrote: > On Wed, Mar 30, 2022 at 5:42 PM Phil Edworthy wrote: > > Details of the SoC can be found here: > > https://www.renesas.com/us/en/products/microcontrollers- > microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai- > accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output > > > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi > > @@ -0,0 +1,99 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +/* > > + * Device Tree Source for the RZ/V2M SoC > > + * > > + * Copyright (C) 2022 Renesas Electronics Corp. > > + */ > > + > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > +#include <dt-bindings/clock/r9a09g011-cpg.h> > > + > > +/ { > > + compatible = "renesas,r9a09g011"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + /* clock can be either from exclk or crystal oscillator > (XIN/XOUT) */ > > + extal_clk: extal { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + /* This value must be overridden by the board */ > > + clock-frequency = <0>; > > + }; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu-map { > > + cluster0 { > > + core0 { > > + cpu = <&cpu0>; > > + }; > > + }; > > + }; > > + > > + cpu0: cpu@0 { > > + compatible = "arm,cortex-a53"; > > + reg = <0>; > > + device_type = "cpu"; > > + clocks = <&cpg CPG_CORE R9A09G011_CA53_CLK>; > > CPG_MOD? Ok > > + }; > > + }; > > + > > + soc: soc { > > + compatible = "simple-bus"; > > + interrupt-parent = <&gic>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + gic: interrupt-controller@82000000 { > > + compatible = "arm,gic-400"; > > + #interrupt-cells = <3>; > > + #address-cells = <0>; > > + interrupt-controller; > > + reg = <0x0 0x82010000 0 0x1000>, > > + <0x0 0x82020000 0 0x20000>, > > + <0x0 0x82040000 0 0x20000>, > > + <0x0 0x82060000 0 0x20000>; > > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) > | IRQ_TYPE_LEVEL_HIGH)>; > > clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>; > clock-names = "clk"; Yes > > + }; > > + > > + cpg: clock-controller@a3500000 { > > + compatible = "renesas,r9a09g011-cpg"; > > + reg = <0 0xa3500000 0 0x10000>; > > Size should be 0x1000, according to the address map. Yes > > + clocks = <&extal_clk>; > > + clock-names = "extal"; > > + #clock-cells = <2>; > > + #reset-cells = <1>; > > + #power-domain-cells = <0>; > > + }; > > + > > + sys: system-configuration@a3f03000 { > > + compatible = "renesas,r9a09g011-sys"; > > system-controller@a3f03000? > > Pending acceptance of the DT bindings. I'll remove this node for the time being. > > + reg = <0 0xa3f03000 0 0x400>; > > + status = "disabled"; > > I think there is no need to keep this disabled. > > > + }; > > + > > + uart0: serial@a4040000 { > > + compatible = "renesas,r9a09g011-uart", > "renesas,em-uart"; > > + reg = <0 0xa4040000 0 0x38>; > > Register offsets are documented until and including 0x7c, > so size should be 0x80 (which matches the address map). Yes > > + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>; > > + clock-names = "sclk"; > > + status = "disabled"; > > + }; > > + }; > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupts-extended = <&gic GIC_PPI 13 > (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > > + <&gic GIC_PPI 14 > (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > > + <&gic GIC_PPI 11 > (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > > + <&gic GIC_PPI 10 > (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; > > + clocks = <&cpg CPG_MOD R9A09G011_SYC_CNT_CLK>; > > + clock-names = "clk"; > > + resets = <&cpg R9A09G011_SYC_RST_N>; > > The three properties above are not document, causing the following > "make dtbs_check" error message: > > arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dtb: timer: > 'clock-names', 'clocks', 'resets' do not match any of the regexes: > 'pinctrl-[0-9]+' > From schema: > Documentation/devicetree/bindings/timer/arm,arch_timer.yaml Right. I assume the correct action is to update the bindings, right? Of course, not much will work without this clock enabled ;) Btw, do you know of a way to run "make dtbs_check" for a single dtb? > > + }; > > +}; Thanks Phil
Hi Phil, On Wed, Apr 27, 2022 at 8:53 PM Phil Edworthy <phil.edworthy@renesas.com> wrote: > On 26 April 2022 19:13 Geert Uytterhoeven wrote: > > On Wed, Mar 30, 2022 at 5:42 PM Phil Edworthy wrote: > > > Details of the SoC can be found here: > > > https://www.renesas.com/us/en/products/microcontrollers- > > microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai- > > accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output > > > > > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> > > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > > > > Thanks for your patch! > > > > > --- /dev/null > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi > > > + timer { > > > + compatible = "arm,armv8-timer"; > > > + interrupts-extended = <&gic GIC_PPI 13 > > (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > > > + <&gic GIC_PPI 14 > > (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > > > + <&gic GIC_PPI 11 > > (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > > > + <&gic GIC_PPI 10 > > (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; > > > + clocks = <&cpg CPG_MOD R9A09G011_SYC_CNT_CLK>; > > > + clock-names = "clk"; > > > + resets = <&cpg R9A09G011_SYC_RST_N>; > > > > The three properties above are not document, causing the following > > "make dtbs_check" error message: > > > > arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dtb: timer: > > 'clock-names', 'clocks', 'resets' do not match any of the regexes: > > 'pinctrl-[0-9]+' > > From schema: > > Documentation/devicetree/bindings/timer/arm,arch_timer.yaml > Right. > I assume the correct action is to update the bindings, right? Yes. > Of course, not much will work without this clock enabled ;) And that's why you have it (rightfully) marked as a critical clock in the clock driver. > Btw, do you know of a way to run "make dtbs_check" for a single dtb? "make dtbs_check" only runs checks on DTBs created by "make dtbs". Hence make sure your .config has only CONFIG_ARCH_R9A09G011 enabled? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi new file mode 100644 index 000000000000..fe1f5107351f --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2M SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r9a09g011-cpg.h> + +/ { + compatible = "renesas,r9a09g011"; + #address-cells = <2>; + #size-cells = <2>; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0>; + device_type = "cpu"; + clocks = <&cpg CPG_CORE R9A09G011_CA53_CLK>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@82000000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x82010000 0 0x1000>, + <0x0 0x82020000 0 0x20000>, + <0x0 0x82040000 0 0x20000>, + <0x0 0x82060000 0 0x20000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + cpg: clock-controller@a3500000 { + compatible = "renesas,r9a09g011-cpg"; + reg = <0 0xa3500000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sys: system-configuration@a3f03000 { + compatible = "renesas,r9a09g011-sys"; + reg = <0 0xa3f03000 0 0x400>; + status = "disabled"; + }; + + uart0: serial@a4040000 { + compatible = "renesas,r9a09g011-uart", "renesas,em-uart"; + reg = <0 0xa4040000 0 0x38>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>; + clock-names = "sclk"; + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + clocks = <&cpg CPG_MOD R9A09G011_SYC_CNT_CLK>; + clock-names = "clk"; + resets = <&cpg R9A09G011_SYC_RST_N>; + }; +};