| Message ID | 20220330154024.112270-14-phil.edworthy@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support | expand |
Hi Phil, On Wed, Mar 30, 2022 at 5:43 PM Phil Edworthy <phil.edworthy@renesas.com> wrote: > Add basic support for RZ/V2M EVK (based on R9A09G011): > - memory > - External input clock > - UART > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Thanks for your patch! > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts > @@ -0,0 +1,45 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/V2M (r9a09g011) Evaluation Kit Board > + * > + * Copyright (C) 2022 Renesas Electronics Corp. > + */ > + > +/dts-v1/; > +#include "r9a09g011.dtsi" > + > +/ { > + model = "RZ/V2M Evaluation Kit 2.0"; > + compatible = "renesas,rzv2mevk2", "renesas,r9a09g011"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory@58000000 { > + device_type = "memory"; > + /* first 128MB is reserved for secure area. */ I guess there's much more reserved for the ISP firmware (1408 MiB?). > + reg = <0x0 0x58000000 0x0 0x28000000>; > + }; > + > + memory@180000000 { > + device_type = "memory"; > + reg = <0x1 0x80000000 0x0 0x80000000>; > + }; > +}; > + > +&extal_clk { > + clock-frequency = <48000000>; > +}; > + > +&sys { > + status = "okay"; > +}; No need to enable sys if it would be enabled by default. > + > +&uart0 { > + status = "okay"; > +}; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index d000f6b131dc..06ba849d3db3 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -79,3 +79,5 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb + +dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts new file mode 100644 index 000000000000..90172de7851f --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2M (r9a09g011) Evaluation Kit Board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a09g011.dtsi" + +/ { + model = "RZ/V2M Evaluation Kit 2.0"; + compatible = "renesas,rzv2mevk2", "renesas,r9a09g011"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@58000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x58000000 0x0 0x28000000>; + }; + + memory@180000000 { + device_type = "memory"; + reg = <0x1 0x80000000 0x0 0x80000000>; + }; +}; + +&extal_clk { + clock-frequency = <48000000>; +}; + +&sys { + status = "okay"; +}; + +&uart0 { + status = "okay"; +};