diff mbox series

[v2,04/13] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC

Message ID 20220330154024.112270-5-phil.edworthy@renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support | expand

Commit Message

Phil Edworthy March 30, 2022, 3:40 p.m. UTC 
Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 .../bindings/clock/renesas,rzg2l-cpg.yaml           | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

Comments

Geert Uytterhoeven April 26, 2022, 2:21 p.m. UTC | #1 
Hi Phil,

On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> @@ -42,9 +44,10 @@ properties:
>      description: |
>        - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
>          and a core clock reference, as defined in
> -        <dt-bindings/clock/r9a07g*-cpg.h>
> +        <dt-bindings/clock/r9a07g*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>

I guess we can simplify to dt-bindings/clock/r9a0*-cpg.h?

The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Phil Edworthy April 26, 2022, 2:39 p.m. UTC | #2 
Hi Geert,

On 26 April 2022 15:21
> On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy wrote:
> > Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
> 
> Thanks for your patch!
> 
> > --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > @@ -42,9 +44,10 @@ properties:
> >      description: |
> >        - For CPG core clocks, the two clock specifier cells must be
> "CPG_CORE"
> >          and a core clock reference, as defined in
> > -        <dt-bindings/clock/r9a07g*-cpg.h>
> > +        <dt-bindings/clock/r9a07g*-cpg.h> or <dt-
> bindings/clock/r9a09g011-cpg.h>
> 
> I guess we can simplify to dt-bindings/clock/r9a0*-cpg.h?
We can, it was just to ensure we don't ever catch a file related
to rz/n1 (r9a06g032). However, r9a06g032 has -sysctrl.h suffix.

I'm easy either way...


> The rest LGTM, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
Thanks!
Phil
Geert Uytterhoeven April 26, 2022, 3 p.m. UTC | #3 
Hi Phil,

On Tue, Apr 26, 2022 at 4:39 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> On 26 April 2022 15:21
> > On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy wrote:
> > > Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC.
> > >
> > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
> >
> > > --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > > +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > > @@ -42,9 +44,10 @@ properties:
> > >      description: |
> > >        - For CPG core clocks, the two clock specifier cells must be
> > "CPG_CORE"
> > >          and a core clock reference, as defined in
> > > -        <dt-bindings/clock/r9a07g*-cpg.h>
> > > +        <dt-bindings/clock/r9a07g*-cpg.h> or <dt-
> > bindings/clock/r9a09g011-cpg.h>
> >
> > I guess we can simplify to dt-bindings/clock/r9a0*-cpg.h?
> We can, it was just to ensure we don't ever catch a file related
> to rz/n1 (r9a06g032). However, r9a06g032 has -sysctrl.h suffix.

Even if RZ/N1 had the -cpg.h suffix, it would fall under different
bindings. Not much we can do anyway, when people include the wrong
header file ;-)

> I'm easy either way...

I'm trying to avoid having to update (too) many places when
adding support for a new SoC.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index bd3af8fc616b..b1145f9139d2 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -4,14 +4,15 @@ 
 $id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
 
-title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
+title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
 
 maintainers:
   - Geert Uytterhoeven <geert+renesas@glider.be>
 
 description: |
   On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
-  Standby Mode share the same register block.
+  Standby Mode share the same register block. On RZ/V2M, the functionality is
+  similar, but does not have Clock Monitor Registers.
 
   They provide the following functionalities:
     - The CPG block generates various core clocks,
@@ -25,6 +26,7 @@  properties:
     enum:
       - renesas,r9a07g044-cpg  # RZ/G2{L,LC}
       - renesas,r9a07g054-cpg  # RZ/V2L
+      - renesas,r9a09g011-cpg  # RZ/V2M
 
   reg:
     maxItems: 1
@@ -42,9 +44,10 @@  properties:
     description: |
       - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
         and a core clock reference, as defined in
-        <dt-bindings/clock/r9a07g*-cpg.h>
+        <dt-bindings/clock/r9a07g*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>
       - For module clocks, the two clock specifier cells must be "CPG_MOD" and
-        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.
+        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or
+        <dt-bindings/clock/r9a09g011-cpg.h>.
     const: 2
 
   '#power-domain-cells':
@@ -58,7 +61,7 @@  properties:
   '#reset-cells':
     description:
       The single reset specifier cell must be the module number, as defined in
-      the <dt-bindings/clock/r9a07g0*-cpg.h>.
+      the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.
     const: 1
 
 required: