From patchwork Tue May 3 11:55:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Edworthy X-Patchwork-Id: 12835696 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13C47C433EF for ; Tue, 3 May 2022 12:02:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234201AbiECMGU (ORCPT ); Tue, 3 May 2022 08:06:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235125AbiECMGM (ORCPT ); Tue, 3 May 2022 08:06:12 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E8620366B5; Tue, 3 May 2022 05:02:33 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,195,1647270000"; d="scan'208";a="118643206" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 03 May 2022 21:02:33 +0900 Received: from localhost.localdomain (unknown [10.226.92.6]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id B409D4226AEF; Tue, 3 May 2022 21:02:30 +0900 (JST) From: Phil Edworthy To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski Cc: Phil Edworthy , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Biju Das Subject: [PATCH v3 11/12] arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC Date: Tue, 3 May 2022 12:55:56 +0100 Message-Id: <20220503115557.53370-12-phil.edworthy@renesas.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220503115557.53370-1-phil.edworthy@renesas.com> References: <20220503115557.53370-1-phil.edworthy@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Details of the SoC can be found here: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v3: - Replace CPG_CORE with CPG_MOD - Add UART pclk - Add gic clk - Fix cpg and uart0 register region - Remove sys as we are currently not using it and binding not accepted --- arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 95 ++++++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g011.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi new file mode 100644 index 000000000000..dafc0837775b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2M SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a09g011"; + #address-cells = <2>; + #size-cells = <2>; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0>; + device_type = "cpu"; + clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@82000000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x82010000 0 0x1000>, + <0x0 0x82020000 0 0x20000>, + <0x0 0x82040000 0 0x20000>, + <0x0 0x82060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>; + clock-names = "clk"; + }; + + cpg: clock-controller@a3500000 { + compatible = "renesas,r9a09g011-cpg"; + reg = <0 0xa3500000 0 0x1000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + uart0: serial@a4040000 { + compatible = "renesas,r9a09g011-uart", "renesas,em-uart"; + reg = <0 0xa4040000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>, + <&cpg CPG_MOD R9A09G011_URT_PCLK>; + clock-names = "sclk", "pclk"; + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + clocks = <&cpg CPG_MOD R9A09G011_SYC_CNT_CLK>; + resets = <&cpg R9A09G011_SYC_RST_N>; + }; +};