From patchwork Tue May 3 11:55:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Edworthy X-Patchwork-Id: 12835690 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E60B9C433EF for ; Tue, 3 May 2022 12:01:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235040AbiECMFC (ORCPT ); Tue, 3 May 2022 08:05:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231795AbiECMFB (ORCPT ); Tue, 3 May 2022 08:05:01 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 694573057C; Tue, 3 May 2022 05:01:29 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,195,1647270000"; d="scan'208";a="119861773" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 03 May 2022 21:01:29 +0900 Received: from localhost.localdomain (unknown [10.226.92.6]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id AA1FA4226915; Tue, 3 May 2022 21:01:25 +0900 (JST) From: Phil Edworthy To: Rob Herring , Krzysztof Kozlowski Cc: Phil Edworthy , Geert Uytterhoeven , Biju Das , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Mark Rutland , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 04/12] dt-bindings: timer: arm,arch_timer: Add optional clock and reset Date: Tue, 3 May 2022 12:55:49 +0100 Message-Id: <20220503115557.53370-5-phil.edworthy@renesas.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220503115557.53370-1-phil.edworthy@renesas.com> References: <20220503115557.53370-1-phil.edworthy@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Some SoCs use a gated clock for the timer and the means to reset the timer. Hence add these as optional. Signed-off-by: Phil Edworthy --- .../devicetree/bindings/timer/arm,arch_timer.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml index df8ce87fd54b..20cd90fc7015 100644 --- a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml @@ -64,6 +64,13 @@ properties: CNTFRQ on all CPUs to a uniform correct value. Use of this property is strongly discouraged; fix your firmware unless absolutely impossible. + clocks: + description: Optional clock for the timer. + maxItems: 1 + + resets: + maxItems: 1 + always-on: type: boolean description: If present, the timer is powered through an always-on power