| Message ID | 20220504145454.71287-7-phil.edworthy@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add Renesas RZ/V2M Ethernet support | expand |
Hello! On 5/4/22 5:54 PM, Phil Edworthy wrote: > RZ/V2M has a separate gPTP reference clock that is used when the > AVB-DMAC Mode Register (CCC) gPTP Clock Select (CSEL) bits are > set to "01: High-speed peripheral bus clock". > Therefore, add a feature that allows this clock to be used for > gPTP. > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru> [...] > diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h > index 73976a392457..f8706897ea41 100644 > --- a/drivers/net/ethernet/renesas/ravb.h > +++ b/drivers/net/ethernet/renesas/ravb.h > @@ -1032,6 +1032,7 @@ struct ravb_hw_info { > unsigned gptp:1; /* AVB-DMAC has gPTP support */ > unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in config mode */ > unsigned gptp_ptm_gic:1; /* gPTP enables Presentation Time Match irq via GIC */ > + unsigned gptp_ref_clk:1; /* gPTP has separate reference clock */ Perhaps just gptp_clk? [...] > @@ -1043,6 +1044,7 @@ struct ravb_private { > void __iomem *addr; > struct clk *clk; > struct clk *refclk; I wonder what that refclk feeds -- no word of it in the commit adding it... > + struct clk *gptp_clk; > struct mdiobb_ctrl mdiobb; > u32 num_rx_ring[NUM_RX_QUEUE]; > u32 num_tx_ring[NUM_TX_QUEUE]; [...] MBR, Sergey
diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index 73976a392457..f8706897ea41 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -1032,6 +1032,7 @@ struct ravb_hw_info { unsigned gptp:1; /* AVB-DMAC has gPTP support */ unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in config mode */ unsigned gptp_ptm_gic:1; /* gPTP enables Presentation Time Match irq via GIC */ + unsigned gptp_ref_clk:1; /* gPTP has separate reference clock */ unsigned nc_queues:1; /* AVB-DMAC has RX and TX NC queues */ unsigned magic_pkt:1; /* E-MAC supports magic packet detection */ unsigned half_duplex:1; /* E-MAC supports half duplex mode */ @@ -1043,6 +1044,7 @@ struct ravb_private { void __iomem *addr; struct clk *clk; struct clk *refclk; + struct clk *gptp_clk; struct mdiobb_ctrl mdiobb; u32 num_rx_ring[NUM_RX_QUEUE]; u32 num_tx_ring[NUM_TX_QUEUE]; diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index f12a23b9c391..ded87cb51650 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2496,11 +2496,15 @@ MODULE_DEVICE_TABLE(of, ravb_match_table); static int ravb_set_gti(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); + const struct ravb_hw_info *info = priv->info; struct device *dev = ndev->dev.parent; unsigned long rate; uint64_t inc; - rate = clk_get_rate(priv->clk); + if (info->gptp_ref_clk) + rate = clk_get_rate(priv->gptp_clk); + else + rate = clk_get_rate(priv->clk); if (!rate) return -EINVAL; @@ -2715,6 +2719,15 @@ static int ravb_probe(struct platform_device *pdev) } clk_prepare_enable(priv->refclk); + if (info->gptp_ref_clk) { + priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); + if (IS_ERR(priv->gptp_clk)) { + error = PTR_ERR(priv->gptp_clk); + goto out_release; + } + clk_prepare_enable(priv->gptp_clk); + } + ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); ndev->min_mtu = ETH_MIN_MTU;