From patchwork Mon May 9 14:24:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Edworthy X-Patchwork-Id: 12843654 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDA5CC433EF for ; Mon, 9 May 2022 14:25:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237185AbiEIO31 (ORCPT ); Mon, 9 May 2022 10:29:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237151AbiEIO3Z (ORCPT ); Mon, 9 May 2022 10:29:25 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 417BB1F01A6; Mon, 9 May 2022 07:25:30 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,211,1647270000"; d="scan'208";a="120391127" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 09 May 2022 23:25:29 +0900 Received: from localhost.localdomain (unknown [10.226.93.110]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 4D14240078D5; Mon, 9 May 2022 23:25:26 +0900 (JST) From: Phil Edworthy To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: Phil Edworthy , Geert Uytterhoeven , Sergey Shtylyov , Biju Das , Lad Prabhakar , netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 4/5] ravb: Use separate clock for gPTP Date: Mon, 9 May 2022 15:24:30 +0100 Message-Id: <20220509142431.24898-5-phil.edworthy@renesas.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220509142431.24898-1-phil.edworthy@renesas.com> References: <20220509142431.24898-1-phil.edworthy@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org RZ/V2M has a separate gPTP reference clock that is used when the AVB-DMAC Mode Register (CCC) gPTP Clock Select (CSEL) bits are set to "01: High-speed peripheral bus clock". Therefore, add a feature that allows this clock to be used for gPTP. Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Reviewed-by: Sergey Shtylyov ------ v2: - Added Reviewed-by tags --- drivers/net/ethernet/renesas/ravb.h | 2 ++ drivers/net/ethernet/renesas/ravb_main.c | 15 ++++++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index 4832beb0bddc..12360fc38d44 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -1031,6 +1031,7 @@ struct ravb_hw_info { unsigned err_mgmt_irqs:1; /* Line1 (Err) and Line2 (Mgmt) irqs are separate */ unsigned gptp:1; /* AVB-DMAC has gPTP support */ unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in config mode */ + unsigned gptp_ref_clk:1; /* gPTP has separate reference clock */ unsigned nc_queues:1; /* AVB-DMAC has RX and TX NC queues */ unsigned magic_pkt:1; /* E-MAC supports magic packet detection */ unsigned half_duplex:1; /* E-MAC supports half duplex mode */ @@ -1042,6 +1043,7 @@ struct ravb_private { void __iomem *addr; struct clk *clk; struct clk *refclk; + struct clk *gptp_clk; struct mdiobb_ctrl mdiobb; u32 num_rx_ring[NUM_RX_QUEUE]; u32 num_tx_ring[NUM_TX_QUEUE]; diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index d1e1ced33a08..0e1d9fc8a627 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2495,11 +2495,15 @@ MODULE_DEVICE_TABLE(of, ravb_match_table); static int ravb_set_gti(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); + const struct ravb_hw_info *info = priv->info; struct device *dev = ndev->dev.parent; unsigned long rate; uint64_t inc; - rate = clk_get_rate(priv->clk); + if (info->gptp_ref_clk) + rate = clk_get_rate(priv->gptp_clk); + else + rate = clk_get_rate(priv->clk); if (!rate) return -EINVAL; @@ -2721,6 +2725,15 @@ static int ravb_probe(struct platform_device *pdev) } clk_prepare_enable(priv->refclk); + if (info->gptp_ref_clk) { + priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); + if (IS_ERR(priv->gptp_clk)) { + error = PTR_ERR(priv->gptp_clk); + goto out_release; + } + clk_prepare_enable(priv->gptp_clk); + } + ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); ndev->min_mtu = ETH_MIN_MTU;