| Message ID | 20220518172808.1691450-1-ralph.siemsen@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | [1/3] clk: renesas: r9a06g032: Fix UART clkgrp bitsel | expand |
H Ralph, Thanks for the patch! On 18 May 2022 18:27 Ralph Siemsen wrote: > There are two UART clock groups, each having a mux to select its > upstream clock source. The register/bit definitions for accessing these > two muxes appear to have been reversed since introduction. Correct them > so as to match the hardware manual. > > Fixes: 4c3d88526eba ("clk: renesas: Renesas R9A06G032 clock driver") > > Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> > --- > drivers/clk/renesas/r9a06g032-clocks.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/renesas/r9a06g032-clocks.c > b/drivers/clk/renesas/r9a06g032-clocks.c > index c99942f0e4d4..0baa6a06ada8 100644 > --- a/drivers/clk/renesas/r9a06g032-clocks.c > +++ b/drivers/clk/renesas/r9a06g032-clocks.c > @@ -287,7 +287,7 @@ static const struct r9a06g032_clkdesc > r9a06g032_clocks[] = { > .type = K_BITSEL, > .source = 1 + R9A06G032_DIV_UART, > /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */ > - .dual.sel = ((0xec / 4) << 5) | 24, > + .dual.sel = ((0x34 / 4) << 5) | 30, The comment above also needs swapping. > .dual.group = 0, > }, > { > @@ -296,7 +296,7 @@ static const struct r9a06g032_clkdesc > r9a06g032_clocks[] = { > .type = K_BITSEL, > .source = 1 + R9A06G032_DIV_P2_PG, > /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */ > - .dual.sel = ((0x34 / 4) << 5) | 30, > + .dual.sel = ((0xec / 4) << 5) | 24, > .dual.group = 1, > }, > D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, > 0x1b4, 0x1b5), > -- > 2.25.1 With the above change: Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com> Thanks Phil
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index c99942f0e4d4..0baa6a06ada8 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -287,7 +287,7 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { .type = K_BITSEL, .source = 1 + R9A06G032_DIV_UART, /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */ - .dual.sel = ((0xec / 4) << 5) | 24, + .dual.sel = ((0x34 / 4) << 5) | 30, .dual.group = 0, }, { @@ -296,7 +296,7 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { .type = K_BITSEL, .source = 1 + R9A06G032_DIV_P2_PG, /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */ - .dual.sel = ((0x34 / 4) << 5) | 30, + .dual.sel = ((0xec / 4) << 5) | 24, .dual.group = 1, }, D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
There are two UART clock groups, each having a mux to select its upstream clock source. The register/bit definitions for accessing these two muxes appear to have been reversed since introduction. Correct them so as to match the hardware manual. Fixes: 4c3d88526eba ("clk: renesas: Renesas R9A06G032 clock driver") Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> --- drivers/clk/renesas/r9a06g032-clocks.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)