From patchwork Thu May 19 15:31:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 12855329 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B9EAC433F5 for ; Thu, 19 May 2022 15:33:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241125AbiESPdL (ORCPT ); Thu, 19 May 2022 11:33:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241075AbiESPdA (ORCPT ); Thu, 19 May 2022 11:33:00 -0400 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C3B162BE2; Thu, 19 May 2022 08:32:53 -0700 (PDT) Received: (Authenticated sender: clement.leger@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 8D105FF806; Thu, 19 May 2022 15:32:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1652974372; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oL5qawJmkUzS7o+kdJIgpH3uP+moAKieArFVw9WPNlU=; b=oG2qRw0GXw72svAMipta0NXey9MEtERPCAQUV8k3ByocdfoZ7zpog7XkkTKemEXNWXQxf6 gZsndjgm8BKJ1yiKotVn63+ZnaKZylctmMZPNU/XzVAaUtOWjdPhXafruy9AbCY/khtVs6 lWBzEfS3H5ZdTpZ1I1P2hwcrgrKV3KpOlvR9IdsO2QGQ4aZHU6Nc/geXGUM9ybqcAYWVUR YcVeJUdWT+leHKqffuiaHaGvKuqvrqxsmLN2RmV/+582M5QcIinwn2T6F8N/BWqRp7cyKF ECy4ZxP9Su+UgterehPbcIt2roS0aLeF/Ch1154XEfkYi+iAKD3XTD7UFmivmg== From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Heiner Kallweit , Russell King Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Thomas Petazzoni , Herve Codina , =?utf-8?q?Miqu=C3=A8l_Raynal?= , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH net-next v5 11/13] ARM: dts: r9a06g032: describe GMAC2 Date: Thu, 19 May 2022 17:31:05 +0200 Message-Id: <20220519153107.696864-12-clement.leger@bootlin.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220519153107.696864-1-clement.leger@bootlin.com> References: <20220519153107.696864-1-clement.leger@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org RZ/N1 SoC includes two MAC named GMACx that are compatible with the "snps,dwmac" driver. GMAC1 is connected directly to the MII converter port 1. GMAC2 however can be used as the MAC for the switch CPU management port or can be muxed to be connected directly to the MII converter port 2. This commit add description for the GMAC2 which will be used by the switch description. Signed-off-by: Clément Léger --- arch/arm/boot/dts/r9a06g032.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 0051fe9f44fd..31c4b2e2950a 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -200,6 +200,23 @@ nand_controller: nand-controller@40102000 { status = "disabled"; }; + gmac2: ethernet@44002000 { + compatible = "snps,dwmac"; + reg = <0x44002000 0x2000>; + interrupt-parent = <&gic>; + interrupts = , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + clock-names = "stmmaceth"; + clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; + status = "disabled"; + }; + eth_miic: eth-miic@44030000 { compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; #address-cells = <1>;