From patchwork Mon Jun 27 05:12:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12896201 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3422CCA47E for ; Mon, 27 Jun 2022 05:13:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231635AbiF0FNE (ORCPT ); Mon, 27 Jun 2022 01:13:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231351AbiF0FNC (ORCPT ); Mon, 27 Jun 2022 01:13:02 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90F013888; Sun, 26 Jun 2022 22:13:01 -0700 (PDT) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 005F65C019D; Mon, 27 Jun 2022 01:13:01 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute1.internal (MEProxy); Mon, 27 Jun 2022 01:13:01 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm3; t=1656306780; x= 1656393180; bh=6AYLrxKS1kGzYaCKlRypTFspscTKmPnJSs3erP6wz1w=; b=k dOF4mlRrncMvmxqTBXFJv0uZzvqiAuA+WGEzPTn1W4cS/eLTvrJDBvrEZZp2bSwZ u8/u7FBDthN7jNyokEAYT9XDrp57cBNVFkxbzELBBeVpTl4PKRfPYfZ9EWzrEvEL mNapWNuvdj65vengO3Q33z9Csoim9rZ6aUYx704JQrdrzeLc5j3/X9MJBwD30gOl OT2ZdySuFgrZag3Fum3cqIQn9DrkZq+1gt27KmR/m6kLAhRtJOEfCAwabJpC5+Y2 jewJHdzY51M/RV1VykQ5FcXQ4+7H9mFxrN2Q7apOUOEKd3Y5GmtI6diXBfjG0NFw DGTU/YyVdMUZBHPvUadfA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm2; t=1656306780; x= 1656393180; bh=6AYLrxKS1kGzYaCKlRypTFspscTKmPnJSs3erP6wz1w=; b=E shgTd6PCY3pBsBTMsG1M4fmh046VCXqVhwm76Mn1oFAI53fiehbtRxEGH/xj4jYt Rq6Vmk1fh56mWkECA6TugPJBhiw3PhdDjUHnkmc/Cm4gNf8Y/QJII1XuFmYJ0aqu LUUSJ8feloAHkrGq7CcT82KL3D6QtvDmdTUn3r/EODHfQ8vsGfl0sJneLiqsk/Zb wc9Q53+dZpq2hcqlBA72o4jBWK4yvXNrEJUGcEqysqs+jmx47CIv3/Aa0BJ29EYw fz+aIJCmbX5bcqZLtZxJd45PiZ3s1JRDT1dFE0V9Wlu71zB9T0XDb/kGGe/QfQcu n0YFwQ+R+SYDG8WmW8xzg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrudeggedgkeelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhggtgfgsehtkeertdertdejnecuhfhrohhmpefurghm uhgvlhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenuc ggtffrrghtthgvrhhnpeefueevueeffeelheelhfelgeelgffgieekffevteefveejueei teeugfefieehleenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfh hrohhmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 27 Jun 2022 01:13:00 -0400 (EDT) From: Samuel Holland To: Lad Prabhakar , Prabhakar , Marc Zyngier , Sagar Kadam , Paul Walmsley , Palmer Dabbelt Cc: linux-renesas-soc@vger.kernel.org, Guo Ren , Geert Uytterhoeven , Thomas Gleixner , Biju Das , Samuel Holland , Albert Ou , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v1 1/3] dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC Date: Mon, 27 Jun 2022 00:12:55 -0500 Message-Id: <20220627051257.38543-2-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220627051257.38543-1-samuel@sholland.org> References: <20220627051257.38543-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The RISC-V PLIC specification unfortunately allows PLIC implementations to ignore edges seen while an edge-triggered interrupt is being handled: Depending on the design of the device and the interrupt handler, in between sending an interrupt request and receiving notice of its handler’s completion, the gateway might either ignore additional matching edges or increment a counter of pending interrupts. For PLICs with that misfeature, software needs to know the trigger type of each interrupt. This allows it to work around the issue by completing edge-triggered interrupts before handling them. Such a workaround is required to avoid missing any edges. The T-HEAD C9xx PLIC is an example of a PLIC with this behavior. Signed-off-by: Samuel Holland Reviewed-by: Guo Ren --- .../sifive,plic-1.0.0.yaml | 31 ++++++++++++++++--- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 27092c6a86c4..3c589cbca851 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -26,9 +26,13 @@ description: with priority below this threshold will not cause the PLIC to raise its interrupt line leading to the context. - While the PLIC supports both edge-triggered and level-triggered interrupts, - interrupt handlers are oblivious to this distinction and therefore it is not - specified in the PLIC device-tree binding. + The PLIC supports both edge-triggered and level-triggered interrupts. For + edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges + seen while an interrupt handler is active; the PLIC may either queue them or + ignore them. In the first case, handlers are oblivious to the trigger type, so + it is not included in the interrupt specifier. In the second case, software + needs to know the trigger type, so it can reorder the interrupt flow to avoid + missing interrupts. While the RISC-V ISA doesn't specify a memory layout for the PLIC, the "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that @@ -65,7 +69,8 @@ properties: const: 0 '#interrupt-cells': - const: 1 + minimum: 1 + maximum: 2 interrupt-controller: true @@ -91,6 +96,24 @@ required: - interrupts-extended - riscv,ndev +allOf: + - if: + properties: + compatible: + contains: + enum: + - thead,c900-plic + + then: + properties: + '#interrupt-cells': + const: 2 + + else: + properties: + '#interrupt-cells': + const: 1 + additionalProperties: false examples: