| Message ID | 20220718195651.7711-6-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add IRQC support to Renesas RZ/G2L and RZ/V2L SoC | expand |
Hi Prabhakar, On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0 > and ETH1 respectively. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 { > compatible = "ethernet-phy-id0022.1640", > "ethernet-phy-ieee802.3-c22"; > reg = <7>; > + interrupt-parent = <&irqc>; > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 2? "The first cell should contain external interrupt number (IRQ0-7)" > rxc-skew-psec = <2400>; > txc-skew-psec = <2400>; > rxdv-skew-psec = <0>; > @@ -120,6 +122,8 @@ phy1: ethernet-phy@7 { > compatible = "ethernet-phy-id0022.1640", > "ethernet-phy-ieee802.3-c22"; > reg = <7>; > + interrupt-parent = <&irqc>; > + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 3? > rxc-skew-psec = <2400>; > txc-skew-psec = <2400>; > rxdv-skew-psec = <0>; > @@ -171,7 +175,8 @@ eth0_pins: eth0 { > <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ > <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ > <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ > - <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ > + <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */ > + <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */ > }; > > eth1_pins: eth1 { > @@ -189,7 +194,8 @@ eth1_pins: eth1 { > <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */ > <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */ > <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */ > - <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */ > + <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */ > + <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */ > }; > > gpio-sd0-pwr-en-hog { > -- > 2.25.1 >
Hi Geert, Thank you for the review. On Thu, Jul 21, 2022 at 11:47 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0 > > and ETH1 respectively. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > > @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 { > > compatible = "ethernet-phy-id0022.1640", > > "ethernet-phy-ieee802.3-c22"; > > reg = <7>; > > + interrupt-parent = <&irqc>; > > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; > > 2? > IRQ2 = SPI 3, the driver expects the SPI number and is used as index [0] to map the interrupt in the GIC. [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?h=next-20220720#n291 > "The first cell should contain external interrupt number (IRQ0-7)" > Probably I need to reword this to "The first cell should contain the SPI number for IRQ0-7/NMI interrupt lines" ? > > rxc-skew-psec = <2400>; > > txc-skew-psec = <2400>; > > rxdv-skew-psec = <0>; > > @@ -120,6 +122,8 @@ phy1: ethernet-phy@7 { > > compatible = "ethernet-phy-id0022.1640", > > "ethernet-phy-ieee802.3-c22"; > > reg = <7>; > > + interrupt-parent = <&irqc>; > > + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; > > 3? > IRQ3 = SPI 4 Cheers, Prabhakar > > rxc-skew-psec = <2400>; > > txc-skew-psec = <2400>; > > rxdv-skew-psec = <0>; > > @@ -171,7 +175,8 @@ eth0_pins: eth0 { > > <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ > > <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ > > <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ > > - <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ > > + <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */ > > + <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */ > > }; > > > > eth1_pins: eth1 { > > @@ -189,7 +194,8 @@ eth1_pins: eth1 { > > <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */ > > <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */ > > <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */ > > - <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */ > > + <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */ > > + <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */ > > }; > > > > gpio-sd0-pwr-en-hog { > > -- > > 2.25.1 > > > > > -- > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
Hi Prabhakar, On Thu, Jul 21, 2022 at 1:07 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Thu, Jul 21, 2022 at 11:47 AM Geert Uytterhoeven > <geert@linux-m68k.org> wrote: > > On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0 > > > and ETH1 respectively. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Thanks for your patch! > > > > > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > > > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > > > @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 { > > > compatible = "ethernet-phy-id0022.1640", > > > "ethernet-phy-ieee802.3-c22"; > > > reg = <7>; > > > + interrupt-parent = <&irqc>; > > > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; > > > > 2? > > > IRQ2 = SPI 3, the driver expects the SPI number and is used as index > [0] to map the interrupt in the GIC. > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?h=next-20220720#n291 Using the SPI number sounds strange to me, as the consumer (Ethernet PHY) is linked to the IRQC, not to the GIC directly. > > "The first cell should contain external interrupt number (IRQ0-7)" > > > Probably I need to reword this to "The first cell should contain the > SPI number for IRQ0-7/NMI interrupt lines" ? Oh, so zero is the NMI? And 1-8 are IRQ0-7. All of this should be documented in the bindings. Probably you want to document the parent interrupts: - First entry is NMI, - Next 8 entries are IRQ0-7, - Next 32 entries are TINT0-31. Currently it's a flat list. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, On Thu, Jul 21, 2022 at 12:43 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Thu, Jul 21, 2022 at 1:07 PM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Thu, Jul 21, 2022 at 11:47 AM Geert Uytterhoeven > > <geert@linux-m68k.org> wrote: > > > On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0 > > > > and ETH1 respectively. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Thanks for your patch! > > > > > > > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > > > > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > > > > @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 { > > > > compatible = "ethernet-phy-id0022.1640", > > > > "ethernet-phy-ieee802.3-c22"; > > > > reg = <7>; > > > > + interrupt-parent = <&irqc>; > > > > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; > > > > > > 2? > > > > > IRQ2 = SPI 3, the driver expects the SPI number and is used as index > > [0] to map the interrupt in the GIC. > > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?h=next-20220720#n291 > > Using the SPI number sounds strange to me, as the consumer > (Ethernet PHY) is linked to the IRQC, not to the GIC directly. > Right, are you suggesting that I tweak the driver? The other problem is how do we differentiate NMI and IRQ0? How about we add macros for IRQ0-7 and use them in the DTS? > > > "The first cell should contain external interrupt number (IRQ0-7)" > > > > > Probably I need to reword this to "The first cell should contain the > > SPI number for IRQ0-7/NMI interrupt lines" ? > > Oh, so zero is the NMI? > And 1-8 are IRQ0-7. > Yes that's right. > All of this should be documented in the bindings. > > Probably you want to document the parent interrupts: > - First entry is NMI, > - Next 8 entries are IRQ0-7, > - Next 32 entries are TINT0-31. > Currently it's a flat list. > Agreed, I will update that. Cheers, Prabhakar > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
Hi Prabhakar, On Thu, Jul 21, 2022 at 1:55 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Thu, Jul 21, 2022 at 12:43 PM Geert Uytterhoeven > <geert@linux-m68k.org> wrote: > > On Thu, Jul 21, 2022 at 1:07 PM Lad, Prabhakar > > <prabhakar.csengg@gmail.com> wrote: > > > On Thu, Jul 21, 2022 at 11:47 AM Geert Uytterhoeven > > > <geert@linux-m68k.org> wrote: > > > > On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > > > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0 > > > > > and ETH1 respectively. > > > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Thanks for your patch! > > > > > > > > > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > > > > > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > > > > > @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 { > > > > > compatible = "ethernet-phy-id0022.1640", > > > > > "ethernet-phy-ieee802.3-c22"; > > > > > reg = <7>; > > > > > + interrupt-parent = <&irqc>; > > > > > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; > > > > > > > > 2? > > > > > > > IRQ2 = SPI 3, the driver expects the SPI number and is used as index > > > [0] to map the interrupt in the GIC. > > > > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?h=next-20220720#n291 > > > > Using the SPI number sounds strange to me, as the consumer > > (Ethernet PHY) is linked to the IRQC, not to the GIC directly. > > > Right, are you suggesting that I tweak the driver? The other problem > is how do we differentiate NMI and IRQ0? How about we add macros for > IRQ0-7 and use them in the DTS? > > > > > "The first cell should contain external interrupt number (IRQ0-7)" > > > > > > > Probably I need to reword this to "The first cell should contain the > > > SPI number for IRQ0-7/NMI interrupt lines" ? > > > > Oh, so zero is the NMI? > > And 1-8 are IRQ0-7. > > > Yes that's right. I don't think it was ever mentioned that the NMI was exposed, too. Using macros sounds fine to me. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, On Thu, Jul 21, 2022 at 12:59 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Thu, Jul 21, 2022 at 1:55 PM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Thu, Jul 21, 2022 at 12:43 PM Geert Uytterhoeven > > <geert@linux-m68k.org> wrote: > > > On Thu, Jul 21, 2022 at 1:07 PM Lad, Prabhakar > > > <prabhakar.csengg@gmail.com> wrote: > > > > On Thu, Jul 21, 2022 at 11:47 AM Geert Uytterhoeven > > > > <geert@linux-m68k.org> wrote: > > > > > On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > > > > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0 > > > > > > and ETH1 respectively. > > > > > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > Thanks for your patch! > > > > > > > > > > > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > > > > > > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > > > > > > @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 { > > > > > > compatible = "ethernet-phy-id0022.1640", > > > > > > "ethernet-phy-ieee802.3-c22"; > > > > > > reg = <7>; > > > > > > + interrupt-parent = <&irqc>; > > > > > > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; > > > > > > > > > > 2? > > > > > > > > > IRQ2 = SPI 3, the driver expects the SPI number and is used as index > > > > [0] to map the interrupt in the GIC. > > > > > > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?h=next-20220720#n291 > > > > > > Using the SPI number sounds strange to me, as the consumer > > > (Ethernet PHY) is linked to the IRQC, not to the GIC directly. > > > > > Right, are you suggesting that I tweak the driver? The other problem > > is how do we differentiate NMI and IRQ0? How about we add macros for > > IRQ0-7 and use them in the DTS? > > > > > > > "The first cell should contain external interrupt number (IRQ0-7)" > > > > > > > > > Probably I need to reword this to "The first cell should contain the > > > > SPI number for IRQ0-7/NMI interrupt lines" ? > > > > > > Oh, so zero is the NMI? > > > And 1-8 are IRQ0-7. > > > > > Yes that's right. > > I don't think it was ever mentioned that the NMI was exposed, too. > Sorry for not making this clearer. > Using macros sounds fine to me. > Ok, I will send a v2 (just this patch alone) with the macros added as a separate patch in rzg2l-pinctrl.h? Cheers, Prabhakar > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 9410796c8ad6..f15d093fc6de 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -120,6 +122,8 @@ phy1: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -171,7 +175,8 @@ eth0_pins: eth0 { <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ - <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */ }; eth1_pins: eth1 { @@ -189,7 +194,8 @@ eth1_pins: eth1 { <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */ <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */ <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */ - <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */ + <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */ + <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */ }; gpio-sd0-pwr-en-hog {
The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0 and ETH1 respectively. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)